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authorRoland Dreier <rolandd@cisco.com>2007-05-08 21:00:38 -0400
committerRoland Dreier <rolandd@cisco.com>2007-05-08 21:00:38 -0400
commit225c7b1feef1b41170f7037a5b10a65cd8a42c54 (patch)
tree702a0a2cbba7f1c5b2949d236b4463d486204fdc /include/linux/mlx4/device.h
parent1bf66a30421ca772820f489d88c16d0c430d6a67 (diff)
IB/mlx4: Add a driver Mellanox ConnectX InfiniBand adapters
Add an InfiniBand driver for Mellanox ConnectX adapters. Because these adapters can also be used as ethernet NICs and Fibre Channel HBAs, the driver is split into two modules: mlx4_core: Handles low-level things like device initialization and processing firmware commands. Also controls resource allocation so that the InfiniBand, ethernet and FC functions can share a device without stepping on each other. mlx4_ib: Handles InfiniBand-specific things; plugs into the InfiniBand midlayer. Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'include/linux/mlx4/device.h')
-rw-r--r--include/linux/mlx4/device.h331
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diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
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1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/pci.h>
37#include <linux/completion.h>
38#include <linux/radix-tree.h>
39
40#include <asm/atomic.h>
41
42enum {
43 MLX4_FLAG_MSI_X = 1 << 0,
44};
45
46enum {
47 MLX4_MAX_PORTS = 2
48};
49
50enum {
51 MLX4_DEV_CAP_FLAG_RC = 1 << 0,
52 MLX4_DEV_CAP_FLAG_UC = 1 << 1,
53 MLX4_DEV_CAP_FLAG_UD = 1 << 2,
54 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
55 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
56 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
57 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
58 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
59 MLX4_DEV_CAP_FLAG_APM = 1 << 17,
60 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
61 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
62 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
63 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21
64};
65
66enum mlx4_event {
67 MLX4_EVENT_TYPE_COMP = 0x00,
68 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
69 MLX4_EVENT_TYPE_COMM_EST = 0x02,
70 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
71 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
72 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
73 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
74 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
75 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
76 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
77 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
78 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
79 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
80 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
81 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
82 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
83 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
84 MLX4_EVENT_TYPE_CMD = 0x0a
85};
86
87enum {
88 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
89 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
90};
91
92enum {
93 MLX4_PERM_LOCAL_READ = 1 << 10,
94 MLX4_PERM_LOCAL_WRITE = 1 << 11,
95 MLX4_PERM_REMOTE_READ = 1 << 12,
96 MLX4_PERM_REMOTE_WRITE = 1 << 13,
97 MLX4_PERM_ATOMIC = 1 << 14
98};
99
100enum {
101 MLX4_OPCODE_NOP = 0x00,
102 MLX4_OPCODE_SEND_INVAL = 0x01,
103 MLX4_OPCODE_RDMA_WRITE = 0x08,
104 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
105 MLX4_OPCODE_SEND = 0x0a,
106 MLX4_OPCODE_SEND_IMM = 0x0b,
107 MLX4_OPCODE_LSO = 0x0e,
108 MLX4_OPCODE_RDMA_READ = 0x10,
109 MLX4_OPCODE_ATOMIC_CS = 0x11,
110 MLX4_OPCODE_ATOMIC_FA = 0x12,
111 MLX4_OPCODE_ATOMIC_MASK_CS = 0x14,
112 MLX4_OPCODE_ATOMIC_MASK_FA = 0x15,
113 MLX4_OPCODE_BIND_MW = 0x18,
114 MLX4_OPCODE_FMR = 0x19,
115 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
116 MLX4_OPCODE_CONFIG_CMD = 0x1f,
117
118 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
119 MLX4_RECV_OPCODE_SEND = 0x01,
120 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
121 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
122
123 MLX4_CQE_OPCODE_ERROR = 0x1e,
124 MLX4_CQE_OPCODE_RESIZE = 0x16,
125};
126
127enum {
128 MLX4_STAT_RATE_OFFSET = 5
129};
130
131struct mlx4_caps {
132 u64 fw_ver;
133 int num_ports;
134 int vl_cap;
135 int mtu_cap;
136 int gid_table_len;
137 int pkey_table_len;
138 int local_ca_ack_delay;
139 int num_uars;
140 int bf_reg_size;
141 int bf_regs_per_page;
142 int max_sq_sg;
143 int max_rq_sg;
144 int num_qps;
145 int max_wqes;
146 int max_sq_desc_sz;
147 int max_rq_desc_sz;
148 int max_qp_init_rdma;
149 int max_qp_dest_rdma;
150 int reserved_qps;
151 int sqp_start;
152 int num_srqs;
153 int max_srq_wqes;
154 int max_srq_sge;
155 int reserved_srqs;
156 int num_cqs;
157 int max_cqes;
158 int reserved_cqs;
159 int num_eqs;
160 int reserved_eqs;
161 int num_mpts;
162 int num_mtt_segs;
163 int fmr_reserved_mtts;
164 int reserved_mtts;
165 int reserved_mrws;
166 int reserved_uars;
167 int num_mgms;
168 int num_amgms;
169 int reserved_mcgs;
170 int num_qp_per_mgm;
171 int num_pds;
172 int reserved_pds;
173 int mtt_entry_sz;
174 u32 page_size_cap;
175 u32 flags;
176 u16 stat_rate_support;
177 u8 port_width_cap;
178};
179
180struct mlx4_buf_list {
181 void *buf;
182 dma_addr_t map;
183};
184
185struct mlx4_buf {
186 union {
187 struct mlx4_buf_list direct;
188 struct mlx4_buf_list *page_list;
189 } u;
190 int nbufs;
191 int npages;
192 int page_shift;
193};
194
195struct mlx4_mtt {
196 u32 first_seg;
197 int order;
198 int page_shift;
199};
200
201struct mlx4_mr {
202 struct mlx4_mtt mtt;
203 u64 iova;
204 u64 size;
205 u32 key;
206 u32 pd;
207 u32 access;
208 int enabled;
209};
210
211struct mlx4_uar {
212 unsigned long pfn;
213 int index;
214};
215
216struct mlx4_cq {
217 void (*comp) (struct mlx4_cq *);
218 void (*event) (struct mlx4_cq *, enum mlx4_event);
219
220 struct mlx4_uar *uar;
221
222 u32 cons_index;
223
224 __be32 *set_ci_db;
225 __be32 *arm_db;
226 int arm_sn;
227
228 int cqn;
229
230 atomic_t refcount;
231 struct completion free;
232};
233
234struct mlx4_qp {
235 void (*event) (struct mlx4_qp *, enum mlx4_event);
236
237 int qpn;
238
239 atomic_t refcount;
240 struct completion free;
241};
242
243struct mlx4_srq {
244 void (*event) (struct mlx4_srq *, enum mlx4_event);
245
246 int srqn;
247 int max;
248 int max_gs;
249 int wqe_shift;
250
251 atomic_t refcount;
252 struct completion free;
253};
254
255struct mlx4_av {
256 __be32 port_pd;
257 u8 reserved1;
258 u8 g_slid;
259 __be16 dlid;
260 u8 reserved2;
261 u8 gid_index;
262 u8 stat_rate;
263 u8 hop_limit;
264 __be32 sl_tclass_flowlabel;
265 u8 dgid[16];
266};
267
268struct mlx4_dev {
269 struct pci_dev *pdev;
270 unsigned long flags;
271 struct mlx4_caps caps;
272 struct radix_tree_root qp_table_tree;
273};
274
275struct mlx4_init_port_param {
276 int set_guid0;
277 int set_node_guid;
278 int set_si_guid;
279 u16 mtu;
280 int port_width_cap;
281 u16 vl_cap;
282 u16 max_gid;
283 u16 max_pkey;
284 u64 guid0;
285 u64 node_guid;
286 u64 si_guid;
287};
288
289int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
290 struct mlx4_buf *buf);
291void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
292
293int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
294void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
295
296int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
297void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
298
299int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
300 struct mlx4_mtt *mtt);
301void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
302u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
303
304int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
305 int npages, int page_shift, struct mlx4_mr *mr);
306void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
307int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
308int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
309 int start_index, int npages, u64 *page_list);
310int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
311 struct mlx4_buf *buf);
312
313int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
314 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq);
315void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
316
317int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp);
318void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
319
320int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
321 u64 db_rec, struct mlx4_srq *srq);
322void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
323int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
324
325int mlx4_INIT_PORT(struct mlx4_dev *dev, struct mlx4_init_port_param *param, int port);
326int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
327
328int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
329int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
330
331#endif /* MLX4_DEVICE_H */
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