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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2011-02-01 00:16:22 -0500
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2011-02-01 00:16:22 -0500
commita1f3d4bba8ea395a39d34ade6017afee8be16031 (patch)
tree874d843d35622f17aa6c3e048e42cf0d679bcb75 /include/linux/mfd
parent723d928417bffff6467da155d8ebbbe016464012 (diff)
parentebf53826e105f488f4f628703a108e98940d1dc5 (diff)
Merge commit 'v2.6.38-rc3' into next
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/ab8500.h58
-rw-r--r--include/linux/mfd/core.h8
-rw-r--r--include/linux/mfd/max8998-private.h2
-rw-r--r--include/linux/mfd/max8998.h31
-rw-r--r--include/linux/mfd/mc13783.h67
-rw-r--r--include/linux/mfd/mc13892.h39
-rw-r--r--include/linux/mfd/tc35892.h136
-rw-r--r--include/linux/mfd/tc3589x.h195
-rw-r--r--include/linux/mfd/tmio.h5
-rw-r--r--include/linux/mfd/wl1273-core.h288
-rw-r--r--include/linux/mfd/wm831x/core.h1
-rw-r--r--include/linux/mfd/wm8350/audio.h3
-rw-r--r--include/linux/mfd/wm8994/core.h8
-rw-r--r--include/linux/mfd/wm8994/pdata.h19
-rw-r--r--include/linux/mfd/wm8994/registers.h302
15 files changed, 956 insertions, 206 deletions
diff --git a/include/linux/mfd/ab8500.h b/include/linux/mfd/ab8500.h
index d63b6050b183..37f56b7c4c15 100644
--- a/include/linux/mfd/ab8500.h
+++ b/include/linux/mfd/ab8500.h
@@ -74,32 +74,37 @@
74#define AB8500_INT_ACC_DETECT_21DB_F 37 74#define AB8500_INT_ACC_DETECT_21DB_F 37
75#define AB8500_INT_ACC_DETECT_21DB_R 38 75#define AB8500_INT_ACC_DETECT_21DB_R 38
76#define AB8500_INT_GP_SW_ADC_CONV_END 39 76#define AB8500_INT_GP_SW_ADC_CONV_END 39
77#define AB8500_INT_BTEMP_LOW 72 77#define AB8500_INT_ADP_SOURCE_ERROR 72
78#define AB8500_INT_BTEMP_LOW_MEDIUM 73 78#define AB8500_INT_ADP_SINK_ERROR 73
79#define AB8500_INT_BTEMP_MEDIUM_HIGH 74 79#define AB8500_INT_ADP_PROBE_PLUG 74
80#define AB8500_INT_BTEMP_HIGH 75 80#define AB8500_INT_ADP_PROBE_UNPLUG 75
81#define AB8500_INT_USB_CHARGER_NOT_OK 81 81#define AB8500_INT_ADP_SENSE_OFF 76
82#define AB8500_INT_ID_WAKEUP_R 82 82#define AB8500_INT_USB_PHY_POWER_ERR 78
83#define AB8500_INT_ID_DET_R1R 84 83#define AB8500_INT_USB_LINK_STATUS 79
84#define AB8500_INT_ID_DET_R2R 85 84#define AB8500_INT_BTEMP_LOW 80
85#define AB8500_INT_ID_DET_R3R 86 85#define AB8500_INT_BTEMP_LOW_MEDIUM 81
86#define AB8500_INT_ID_DET_R4R 87 86#define AB8500_INT_BTEMP_MEDIUM_HIGH 82
87#define AB8500_INT_ID_WAKEUP_F 88 87#define AB8500_INT_BTEMP_HIGH 83
88#define AB8500_INT_ID_DET_R1F 90 88#define AB8500_INT_USB_CHARGER_NOT_OK 89
89#define AB8500_INT_ID_DET_R2F 91 89#define AB8500_INT_ID_WAKEUP_R 90
90#define AB8500_INT_ID_DET_R3F 92 90#define AB8500_INT_ID_DET_R1R 92
91#define AB8500_INT_ID_DET_R4F 93 91#define AB8500_INT_ID_DET_R2R 93
92#define AB8500_INT_USB_CHG_DET_DONE 94 92#define AB8500_INT_ID_DET_R3R 94
93#define AB8500_INT_USB_CH_TH_PROT_F 96 93#define AB8500_INT_ID_DET_R4R 95
94#define AB8500_INT_USB_CH_TH_PROP_R 97 94#define AB8500_INT_ID_WAKEUP_F 96
95#define AB8500_INT_MAIN_CH_TH_PROP_F 98 95#define AB8500_INT_ID_DET_R1F 98
96#define AB8500_INT_MAIN_CH_TH_PROT_R 99 96#define AB8500_INT_ID_DET_R2F 99
97#define AB8500_INT_USB_CHARGER_NOT_OKF 103 97#define AB8500_INT_ID_DET_R3F 100
98#define AB8500_INT_ID_DET_R4F 101
99#define AB8500_INT_USB_CHG_DET_DONE 102
100#define AB8500_INT_USB_CH_TH_PROT_F 104
101#define AB8500_INT_USB_CH_TH_PROT_R 105
102#define AB8500_INT_MAIN_CH_TH_PROT_F 106
103#define AB8500_INT_MAIN_CH_TH_PROT_R 107
104#define AB8500_INT_USB_CHARGER_NOT_OKF 111
98 105
99#define AB8500_NR_IRQS 104 106#define AB8500_NR_IRQS 112
100#define AB8500_NUM_IRQ_REGS 13 107#define AB8500_NUM_IRQ_REGS 14
101
102#define AB8500_NUM_REGULATORS 15
103 108
104/** 109/**
105 * struct ab8500 - ab8500 internal structure 110 * struct ab8500 - ab8500 internal structure
@@ -145,7 +150,8 @@ struct regulator_init_data;
145struct ab8500_platform_data { 150struct ab8500_platform_data {
146 int irq_base; 151 int irq_base;
147 void (*init) (struct ab8500 *); 152 void (*init) (struct ab8500 *);
148 struct regulator_init_data *regulator[AB8500_NUM_REGULATORS]; 153 int num_regulator;
154 struct regulator_init_data *regulator;
149}; 155};
150 156
151extern int __devinit ab8500_init(struct ab8500 *ab8500); 157extern int __devinit ab8500_init(struct ab8500 *ab8500);
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
index cb93d80aa642..835996e167e1 100644
--- a/include/linux/mfd/core.h
+++ b/include/linux/mfd/core.h
@@ -39,7 +39,7 @@ struct mfd_cell {
39 size_t data_size; 39 size_t data_size;
40 40
41 /* 41 /*
42 * This resources can be specified relatievly to the parent device. 42 * This resources can be specified relatively to the parent device.
43 * For accessing device you should use resources from device 43 * For accessing device you should use resources from device
44 */ 44 */
45 int num_resources; 45 int num_resources;
@@ -47,6 +47,12 @@ struct mfd_cell {
47 47
48 /* don't check for resource conflicts */ 48 /* don't check for resource conflicts */
49 bool ignore_resource_conflicts; 49 bool ignore_resource_conflicts;
50
51 /*
52 * Disable runtime PM callbacks for this subdevice - see
53 * pm_runtime_no_callbacks().
54 */
55 bool pm_runtime_no_callbacks;
50}; 56};
51 57
52extern int mfd_add_devices(struct device *parent, int id, 58extern int mfd_add_devices(struct device *parent, int id,
diff --git a/include/linux/mfd/max8998-private.h b/include/linux/mfd/max8998-private.h
index 7363dea6bbcd..effa5d3b96ae 100644
--- a/include/linux/mfd/max8998-private.h
+++ b/include/linux/mfd/max8998-private.h
@@ -159,10 +159,12 @@ struct max8998_dev {
159 u8 irq_masks_cur[MAX8998_NUM_IRQ_REGS]; 159 u8 irq_masks_cur[MAX8998_NUM_IRQ_REGS];
160 u8 irq_masks_cache[MAX8998_NUM_IRQ_REGS]; 160 u8 irq_masks_cache[MAX8998_NUM_IRQ_REGS];
161 int type; 161 int type;
162 bool wakeup;
162}; 163};
163 164
164int max8998_irq_init(struct max8998_dev *max8998); 165int max8998_irq_init(struct max8998_dev *max8998);
165void max8998_irq_exit(struct max8998_dev *max8998); 166void max8998_irq_exit(struct max8998_dev *max8998);
167int max8998_irq_resume(struct max8998_dev *max8998);
166 168
167extern int max8998_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest); 169extern int max8998_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
168extern int max8998_bulk_read(struct i2c_client *i2c, u8 reg, int count, 170extern int max8998_bulk_read(struct i2c_client *i2c, u8 reg, int count,
diff --git a/include/linux/mfd/max8998.h b/include/linux/mfd/max8998.h
index f8c9f884aff2..61daa167b576 100644
--- a/include/linux/mfd/max8998.h
+++ b/include/linux/mfd/max8998.h
@@ -70,24 +70,43 @@ struct max8998_regulator_data {
70 * @num_regulators: number of regultors used 70 * @num_regulators: number of regultors used
71 * @irq_base: base IRQ number for max8998, required for IRQs 71 * @irq_base: base IRQ number for max8998, required for IRQs
72 * @ono: power onoff IRQ number for max8998 72 * @ono: power onoff IRQ number for max8998
73 * @buck1_max_voltage1: BUCK1 maximum alowed voltage register 1 73 * @buck_voltage_lock: Do NOT change the values of the following six
74 * @buck1_max_voltage2: BUCK1 maximum alowed voltage register 2 74 * registers set by buck?_voltage?. The voltage of BUCK1/2 cannot
75 * @buck2_max_voltage: BUCK2 maximum alowed voltage 75 * be other than the preset values.
76 * @buck1_voltage1: BUCK1 DVS mode 1 voltage register
77 * @buck1_voltage2: BUCK1 DVS mode 2 voltage register
78 * @buck1_voltage3: BUCK1 DVS mode 3 voltage register
79 * @buck1_voltage4: BUCK1 DVS mode 4 voltage register
80 * @buck2_voltage1: BUCK2 DVS mode 1 voltage register
81 * @buck2_voltage2: BUCK2 DVS mode 2 voltage register
76 * @buck1_set1: BUCK1 gpio pin 1 to set output voltage 82 * @buck1_set1: BUCK1 gpio pin 1 to set output voltage
77 * @buck1_set2: BUCK1 gpio pin 2 to set output voltage 83 * @buck1_set2: BUCK1 gpio pin 2 to set output voltage
84 * @buck1_default_idx: Default for BUCK1 gpio pin 1, 2
78 * @buck2_set3: BUCK2 gpio pin to set output voltage 85 * @buck2_set3: BUCK2 gpio pin to set output voltage
86 * @buck2_default_idx: Default for BUCK2 gpio pin.
87 * @wakeup: Allow to wake up from suspend
88 * @rtc_delay: LP3974 RTC chip bug that requires delay after a register
89 * write before reading it.
79 */ 90 */
80struct max8998_platform_data { 91struct max8998_platform_data {
81 struct max8998_regulator_data *regulators; 92 struct max8998_regulator_data *regulators;
82 int num_regulators; 93 int num_regulators;
83 int irq_base; 94 int irq_base;
84 int ono; 95 int ono;
85 int buck1_max_voltage1; 96 bool buck_voltage_lock;
86 int buck1_max_voltage2; 97 int buck1_voltage1;
87 int buck2_max_voltage; 98 int buck1_voltage2;
99 int buck1_voltage3;
100 int buck1_voltage4;
101 int buck2_voltage1;
102 int buck2_voltage2;
88 int buck1_set1; 103 int buck1_set1;
89 int buck1_set2; 104 int buck1_set2;
105 int buck1_default_idx;
90 int buck2_set3; 106 int buck2_set3;
107 int buck2_default_idx;
108 bool wakeup;
109 bool rtc_delay;
91}; 110};
92 111
93#endif /* __LINUX_MFD_MAX8998_H */ 112#endif /* __LINUX_MFD_MAX8998_H */
diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h
index b4c741e352c2..7d0f3d6a0002 100644
--- a/include/linux/mfd/mc13783.h
+++ b/include/linux/mfd/mc13783.h
@@ -1,4 +1,5 @@
1/* 1/*
2 * Copyright 2010 Yong Shen <yong.shen@linaro.org>
2 * Copyright 2009-2010 Pengutronix 3 * Copyright 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> 4 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 * 5 *
@@ -122,39 +123,39 @@ int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
122 unsigned int channel, unsigned int *sample); 123 unsigned int channel, unsigned int *sample);
123 124
124 125
125#define MC13783_SW_SW1A 0 126#define MC13783_REG_SW1A 0
126#define MC13783_SW_SW1B 1 127#define MC13783_REG_SW1B 1
127#define MC13783_SW_SW2A 2 128#define MC13783_REG_SW2A 2
128#define MC13783_SW_SW2B 3 129#define MC13783_REG_SW2B 3
129#define MC13783_SW_SW3 4 130#define MC13783_REG_SW3 4
130#define MC13783_SW_PLL 5 131#define MC13783_REG_PLL 5
131#define MC13783_REGU_VAUDIO 6 132#define MC13783_REG_VAUDIO 6
132#define MC13783_REGU_VIOHI 7 133#define MC13783_REG_VIOHI 7
133#define MC13783_REGU_VIOLO 8 134#define MC13783_REG_VIOLO 8
134#define MC13783_REGU_VDIG 9 135#define MC13783_REG_VDIG 9
135#define MC13783_REGU_VGEN 10 136#define MC13783_REG_VGEN 10
136#define MC13783_REGU_VRFDIG 11 137#define MC13783_REG_VRFDIG 11
137#define MC13783_REGU_VRFREF 12 138#define MC13783_REG_VRFREF 12
138#define MC13783_REGU_VRFCP 13 139#define MC13783_REG_VRFCP 13
139#define MC13783_REGU_VSIM 14 140#define MC13783_REG_VSIM 14
140#define MC13783_REGU_VESIM 15 141#define MC13783_REG_VESIM 15
141#define MC13783_REGU_VCAM 16 142#define MC13783_REG_VCAM 16
142#define MC13783_REGU_VRFBG 17 143#define MC13783_REG_VRFBG 17
143#define MC13783_REGU_VVIB 18 144#define MC13783_REG_VVIB 18
144#define MC13783_REGU_VRF1 19 145#define MC13783_REG_VRF1 19
145#define MC13783_REGU_VRF2 20 146#define MC13783_REG_VRF2 20
146#define MC13783_REGU_VMMC1 21 147#define MC13783_REG_VMMC1 21
147#define MC13783_REGU_VMMC2 22 148#define MC13783_REG_VMMC2 22
148#define MC13783_REGU_GPO1 23 149#define MC13783_REG_GPO1 23
149#define MC13783_REGU_GPO2 24 150#define MC13783_REG_GPO2 24
150#define MC13783_REGU_GPO3 25 151#define MC13783_REG_GPO3 25
151#define MC13783_REGU_GPO4 26 152#define MC13783_REG_GPO4 26
152#define MC13783_REGU_V1 27 153#define MC13783_REG_V1 27
153#define MC13783_REGU_V2 28 154#define MC13783_REG_V2 28
154#define MC13783_REGU_V3 29 155#define MC13783_REG_V3 29
155#define MC13783_REGU_V4 30 156#define MC13783_REG_V4 30
156#define MC13783_REGU_PWGT1SPI 31 157#define MC13783_REG_PWGT1SPI 31
157#define MC13783_REGU_PWGT2SPI 32 158#define MC13783_REG_PWGT2SPI 32
158 159
159#define MC13783_IRQ_ADCDONE MC13XXX_IRQ_ADCDONE 160#define MC13783_IRQ_ADCDONE MC13XXX_IRQ_ADCDONE
160#define MC13783_IRQ_ADCBISDONE MC13XXX_IRQ_ADCBISDONE 161#define MC13783_IRQ_ADCBISDONE MC13XXX_IRQ_ADCBISDONE
diff --git a/include/linux/mfd/mc13892.h b/include/linux/mfd/mc13892.h
new file mode 100644
index 000000000000..a00f2bec178c
--- /dev/null
+++ b/include/linux/mfd/mc13892.h
@@ -0,0 +1,39 @@
1/*
2 * Copyright 2010 Yong Shen <yong.shen@linaro.org>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8
9#ifndef __LINUX_MFD_MC13892_H
10#define __LINUX_MFD_MC13892_H
11
12#include <linux/mfd/mc13xxx.h>
13
14#define MC13892_SW1 0
15#define MC13892_SW2 1
16#define MC13892_SW3 2
17#define MC13892_SW4 3
18#define MC13892_SWBST 4
19#define MC13892_VIOHI 5
20#define MC13892_VPLL 6
21#define MC13892_VDIG 7
22#define MC13892_VSD 8
23#define MC13892_VUSB2 9
24#define MC13892_VVIDEO 10
25#define MC13892_VAUDIO 11
26#define MC13892_VCAM 12
27#define MC13892_VGEN1 13
28#define MC13892_VGEN2 14
29#define MC13892_VGEN3 15
30#define MC13892_VUSB 16
31#define MC13892_GPO1 17
32#define MC13892_GPO2 18
33#define MC13892_GPO3 19
34#define MC13892_GPO4 20
35#define MC13892_PWGT1SPI 21
36#define MC13892_PWGT2SPI 22
37#define MC13892_VCOINCELL 23
38
39#endif
diff --git a/include/linux/mfd/tc35892.h b/include/linux/mfd/tc35892.h
deleted file mode 100644
index eff3094ca84e..000000000000
--- a/include/linux/mfd/tc35892.h
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 */
6
7#ifndef __LINUX_MFD_TC35892_H
8#define __LINUX_MFD_TC35892_H
9
10#include <linux/device.h>
11
12#define TC35892_RSTCTRL_IRQRST (1 << 4)
13#define TC35892_RSTCTRL_TIMRST (1 << 3)
14#define TC35892_RSTCTRL_ROTRST (1 << 2)
15#define TC35892_RSTCTRL_KBDRST (1 << 1)
16#define TC35892_RSTCTRL_GPIRST (1 << 0)
17
18#define TC35892_IRQST 0x91
19
20#define TC35892_MANFCODE_MAGIC 0x03
21#define TC35892_MANFCODE 0x80
22#define TC35892_VERSION 0x81
23#define TC35892_IOCFG 0xA7
24
25#define TC35892_CLKMODE 0x88
26#define TC35892_CLKCFG 0x89
27#define TC35892_CLKEN 0x8A
28
29#define TC35892_RSTCTRL 0x82
30#define TC35892_EXTRSTN 0x83
31#define TC35892_RSTINTCLR 0x84
32
33#define TC35892_GPIOIS0 0xC9
34#define TC35892_GPIOIS1 0xCA
35#define TC35892_GPIOIS2 0xCB
36#define TC35892_GPIOIBE0 0xCC
37#define TC35892_GPIOIBE1 0xCD
38#define TC35892_GPIOIBE2 0xCE
39#define TC35892_GPIOIEV0 0xCF
40#define TC35892_GPIOIEV1 0xD0
41#define TC35892_GPIOIEV2 0xD1
42#define TC35892_GPIOIE0 0xD2
43#define TC35892_GPIOIE1 0xD3
44#define TC35892_GPIOIE2 0xD4
45#define TC35892_GPIORIS0 0xD6
46#define TC35892_GPIORIS1 0xD7
47#define TC35892_GPIORIS2 0xD8
48#define TC35892_GPIOMIS0 0xD9
49#define TC35892_GPIOMIS1 0xDA
50#define TC35892_GPIOMIS2 0xDB
51#define TC35892_GPIOIC0 0xDC
52#define TC35892_GPIOIC1 0xDD
53#define TC35892_GPIOIC2 0xDE
54
55#define TC35892_GPIODATA0 0xC0
56#define TC35892_GPIOMASK0 0xc1
57#define TC35892_GPIODATA1 0xC2
58#define TC35892_GPIOMASK1 0xc3
59#define TC35892_GPIODATA2 0xC4
60#define TC35892_GPIOMASK2 0xC5
61
62#define TC35892_GPIODIR0 0xC6
63#define TC35892_GPIODIR1 0xC7
64#define TC35892_GPIODIR2 0xC8
65
66#define TC35892_GPIOSYNC0 0xE6
67#define TC35892_GPIOSYNC1 0xE7
68#define TC35892_GPIOSYNC2 0xE8
69
70#define TC35892_GPIOWAKE0 0xE9
71#define TC35892_GPIOWAKE1 0xEA
72#define TC35892_GPIOWAKE2 0xEB
73
74#define TC35892_GPIOODM0 0xE0
75#define TC35892_GPIOODE0 0xE1
76#define TC35892_GPIOODM1 0xE2
77#define TC35892_GPIOODE1 0xE3
78#define TC35892_GPIOODM2 0xE4
79#define TC35892_GPIOODE2 0xE5
80
81#define TC35892_INT_GPIIRQ 0
82#define TC35892_INT_TI0IRQ 1
83#define TC35892_INT_TI1IRQ 2
84#define TC35892_INT_TI2IRQ 3
85#define TC35892_INT_ROTIRQ 5
86#define TC35892_INT_KBDIRQ 6
87#define TC35892_INT_PORIRQ 7
88
89#define TC35892_NR_INTERNAL_IRQS 8
90#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x))
91
92struct tc35892 {
93 struct mutex lock;
94 struct device *dev;
95 struct i2c_client *i2c;
96
97 int irq_base;
98 int num_gpio;
99 struct tc35892_platform_data *pdata;
100};
101
102extern int tc35892_reg_write(struct tc35892 *tc35892, u8 reg, u8 data);
103extern int tc35892_reg_read(struct tc35892 *tc35892, u8 reg);
104extern int tc35892_block_read(struct tc35892 *tc35892, u8 reg, u8 length,
105 u8 *values);
106extern int tc35892_block_write(struct tc35892 *tc35892, u8 reg, u8 length,
107 const u8 *values);
108extern int tc35892_set_bits(struct tc35892 *tc35892, u8 reg, u8 mask, u8 val);
109
110/**
111 * struct tc35892_gpio_platform_data - TC35892 GPIO platform data
112 * @gpio_base: first gpio number assigned to TC35892. A maximum of
113 * %TC35892_NR_GPIOS GPIOs will be allocated.
114 * @setup: callback for board-specific initialization
115 * @remove: callback for board-specific teardown
116 */
117struct tc35892_gpio_platform_data {
118 int gpio_base;
119 void (*setup)(struct tc35892 *tc35892, unsigned gpio_base);
120 void (*remove)(struct tc35892 *tc35892, unsigned gpio_base);
121};
122
123/**
124 * struct tc35892_platform_data - TC35892 platform data
125 * @irq_base: base IRQ number. %TC35892_NR_IRQS irqs will be used.
126 * @gpio: GPIO-specific platform data
127 */
128struct tc35892_platform_data {
129 int irq_base;
130 struct tc35892_gpio_platform_data *gpio;
131};
132
133#define TC35892_NR_GPIOS 24
134#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS)
135
136#endif
diff --git a/include/linux/mfd/tc3589x.h b/include/linux/mfd/tc3589x.h
new file mode 100644
index 000000000000..16c76e124f9c
--- /dev/null
+++ b/include/linux/mfd/tc3589x.h
@@ -0,0 +1,195 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 */
6
7#ifndef __LINUX_MFD_TC3589x_H
8#define __LINUX_MFD_TC3589x_H
9
10#include <linux/device.h>
11
12enum tx3589x_block {
13 TC3589x_BLOCK_GPIO = 1 << 0,
14 TC3589x_BLOCK_KEYPAD = 1 << 1,
15};
16
17#define TC3589x_RSTCTRL_IRQRST (1 << 4)
18#define TC3589x_RSTCTRL_TIMRST (1 << 3)
19#define TC3589x_RSTCTRL_ROTRST (1 << 2)
20#define TC3589x_RSTCTRL_KBDRST (1 << 1)
21#define TC3589x_RSTCTRL_GPIRST (1 << 0)
22
23/* Keyboard Configuration Registers */
24#define TC3589x_KBDSETTLE_REG 0x01
25#define TC3589x_KBDBOUNCE 0x02
26#define TC3589x_KBDSIZE 0x03
27#define TC3589x_KBCFG_LSB 0x04
28#define TC3589x_KBCFG_MSB 0x05
29#define TC3589x_KBDIC 0x08
30#define TC3589x_KBDMSK 0x09
31#define TC3589x_EVTCODE_FIFO 0x10
32#define TC3589x_KBDMFS 0x8F
33
34#define TC3589x_IRQST 0x91
35
36#define TC3589x_MANFCODE_MAGIC 0x03
37#define TC3589x_MANFCODE 0x80
38#define TC3589x_VERSION 0x81
39#define TC3589x_IOCFG 0xA7
40
41#define TC3589x_CLKMODE 0x88
42#define TC3589x_CLKCFG 0x89
43#define TC3589x_CLKEN 0x8A
44
45#define TC3589x_RSTCTRL 0x82
46#define TC3589x_EXTRSTN 0x83
47#define TC3589x_RSTINTCLR 0x84
48
49/* Pull up/down configuration registers */
50#define TC3589x_IOCFG 0xA7
51#define TC3589x_IOPULLCFG0_LSB 0xAA
52#define TC3589x_IOPULLCFG0_MSB 0xAB
53#define TC3589x_IOPULLCFG1_LSB 0xAC
54#define TC3589x_IOPULLCFG1_MSB 0xAD
55#define TC3589x_IOPULLCFG2_LSB 0xAE
56
57#define TC3589x_GPIOIS0 0xC9
58#define TC3589x_GPIOIS1 0xCA
59#define TC3589x_GPIOIS2 0xCB
60#define TC3589x_GPIOIBE0 0xCC
61#define TC3589x_GPIOIBE1 0xCD
62#define TC3589x_GPIOIBE2 0xCE
63#define TC3589x_GPIOIEV0 0xCF
64#define TC3589x_GPIOIEV1 0xD0
65#define TC3589x_GPIOIEV2 0xD1
66#define TC3589x_GPIOIE0 0xD2
67#define TC3589x_GPIOIE1 0xD3
68#define TC3589x_GPIOIE2 0xD4
69#define TC3589x_GPIORIS0 0xD6
70#define TC3589x_GPIORIS1 0xD7
71#define TC3589x_GPIORIS2 0xD8
72#define TC3589x_GPIOMIS0 0xD9
73#define TC3589x_GPIOMIS1 0xDA
74#define TC3589x_GPIOMIS2 0xDB
75#define TC3589x_GPIOIC0 0xDC
76#define TC3589x_GPIOIC1 0xDD
77#define TC3589x_GPIOIC2 0xDE
78
79#define TC3589x_GPIODATA0 0xC0
80#define TC3589x_GPIOMASK0 0xc1
81#define TC3589x_GPIODATA1 0xC2
82#define TC3589x_GPIOMASK1 0xc3
83#define TC3589x_GPIODATA2 0xC4
84#define TC3589x_GPIOMASK2 0xC5
85
86#define TC3589x_GPIODIR0 0xC6
87#define TC3589x_GPIODIR1 0xC7
88#define TC3589x_GPIODIR2 0xC8
89
90#define TC3589x_GPIOSYNC0 0xE6
91#define TC3589x_GPIOSYNC1 0xE7
92#define TC3589x_GPIOSYNC2 0xE8
93
94#define TC3589x_GPIOWAKE0 0xE9
95#define TC3589x_GPIOWAKE1 0xEA
96#define TC3589x_GPIOWAKE2 0xEB
97
98#define TC3589x_GPIOODM0 0xE0
99#define TC3589x_GPIOODE0 0xE1
100#define TC3589x_GPIOODM1 0xE2
101#define TC3589x_GPIOODE1 0xE3
102#define TC3589x_GPIOODM2 0xE4
103#define TC3589x_GPIOODE2 0xE5
104
105#define TC3589x_INT_GPIIRQ 0
106#define TC3589x_INT_TI0IRQ 1
107#define TC3589x_INT_TI1IRQ 2
108#define TC3589x_INT_TI2IRQ 3
109#define TC3589x_INT_ROTIRQ 5
110#define TC3589x_INT_KBDIRQ 6
111#define TC3589x_INT_PORIRQ 7
112
113#define TC3589x_NR_INTERNAL_IRQS 8
114#define TC3589x_INT_GPIO(x) (TC3589x_NR_INTERNAL_IRQS + (x))
115
116struct tc3589x {
117 struct mutex lock;
118 struct device *dev;
119 struct i2c_client *i2c;
120
121 int irq_base;
122 int num_gpio;
123 struct tc3589x_platform_data *pdata;
124};
125
126extern int tc3589x_reg_write(struct tc3589x *tc3589x, u8 reg, u8 data);
127extern int tc3589x_reg_read(struct tc3589x *tc3589x, u8 reg);
128extern int tc3589x_block_read(struct tc3589x *tc3589x, u8 reg, u8 length,
129 u8 *values);
130extern int tc3589x_block_write(struct tc3589x *tc3589x, u8 reg, u8 length,
131 const u8 *values);
132extern int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val);
133
134/*
135 * Keypad related platform specific constants
136 * These values may be modified for fine tuning
137 */
138#define TC_KPD_ROWS 0x8
139#define TC_KPD_COLUMNS 0x8
140#define TC_KPD_DEBOUNCE_PERIOD 0xA3
141#define TC_KPD_SETTLE_TIME 0xA3
142
143/**
144 * struct tc35893_platform_data - data structure for platform specific data
145 * @keymap_data: matrix scan code table for keycodes
146 * @krow: mask for available rows, value is 0xFF
147 * @kcol: mask for available columns, value is 0xFF
148 * @debounce_period: platform specific debounce time
149 * @settle_time: platform specific settle down time
150 * @irqtype: type of interrupt, falling or rising edge
151 * @enable_wakeup: specifies if keypad event can wake up system from sleep
152 * @no_autorepeat: flag for auto repetition
153 */
154struct tc3589x_keypad_platform_data {
155 const struct matrix_keymap_data *keymap_data;
156 u8 krow;
157 u8 kcol;
158 u8 debounce_period;
159 u8 settle_time;
160 unsigned long irqtype;
161 bool enable_wakeup;
162 bool no_autorepeat;
163};
164
165/**
166 * struct tc3589x_gpio_platform_data - TC3589x GPIO platform data
167 * @gpio_base: first gpio number assigned to TC3589x. A maximum of
168 * %TC3589x_NR_GPIOS GPIOs will be allocated.
169 * @setup: callback for board-specific initialization
170 * @remove: callback for board-specific teardown
171 */
172struct tc3589x_gpio_platform_data {
173 int gpio_base;
174 void (*setup)(struct tc3589x *tc3589x, unsigned gpio_base);
175 void (*remove)(struct tc3589x *tc3589x, unsigned gpio_base);
176};
177
178/**
179 * struct tc3589x_platform_data - TC3589x platform data
180 * @block: bitmask of blocks to enable (use TC3589x_BLOCK_*)
181 * @irq_base: base IRQ number. %TC3589x_NR_IRQS irqs will be used.
182 * @gpio: GPIO-specific platform data
183 * @keypad: keypad-specific platform data
184 */
185struct tc3589x_platform_data {
186 unsigned int block;
187 int irq_base;
188 struct tc3589x_gpio_platform_data *gpio;
189 const struct tc3589x_keypad_platform_data *keypad;
190};
191
192#define TC3589x_NR_GPIOS 24
193#define TC3589x_NR_IRQS TC3589x_INT_GPIO(TC3589x_NR_GPIOS)
194
195#endif
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index 085f041197dc..8e70310ee945 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -57,6 +57,10 @@
57 * is configured in 4-bit mode. 57 * is configured in 4-bit mode.
58 */ 58 */
59#define TMIO_MMC_BLKSZ_2BYTES (1 << 1) 59#define TMIO_MMC_BLKSZ_2BYTES (1 << 1)
60/*
61 * Some controllers can support SDIO IRQ signalling.
62 */
63#define TMIO_MMC_SDIO_IRQ (1 << 2)
60 64
61int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); 65int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
62int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); 66int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
@@ -66,6 +70,7 @@ void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
66struct tmio_mmc_dma { 70struct tmio_mmc_dma {
67 void *chan_priv_tx; 71 void *chan_priv_tx;
68 void *chan_priv_rx; 72 void *chan_priv_rx;
73 int alignment_shift;
69}; 74};
70 75
71/* 76/*
diff --git a/include/linux/mfd/wl1273-core.h b/include/linux/mfd/wl1273-core.h
new file mode 100644
index 000000000000..9787293eae5f
--- /dev/null
+++ b/include/linux/mfd/wl1273-core.h
@@ -0,0 +1,288 @@
1/*
2 * include/linux/mfd/wl1273-core.h
3 *
4 * Some definitions for the wl1273 radio receiver/transmitter chip.
5 *
6 * Copyright (C) 2010 Nokia Corporation
7 * Author: Matti J. Aaltonen <matti.j.aaltonen@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 */
23
24#ifndef WL1273_CORE_H
25#define WL1273_CORE_H
26
27#include <linux/i2c.h>
28#include <linux/mfd/core.h>
29
30#define WL1273_FM_DRIVER_NAME "wl1273-fm"
31#define RX71_FM_I2C_ADDR 0x22
32
33#define WL1273_STEREO_GET 0
34#define WL1273_RSSI_LVL_GET 1
35#define WL1273_IF_COUNT_GET 2
36#define WL1273_FLAG_GET 3
37#define WL1273_RDS_SYNC_GET 4
38#define WL1273_RDS_DATA_GET 5
39#define WL1273_FREQ_SET 10
40#define WL1273_AF_FREQ_SET 11
41#define WL1273_MOST_MODE_SET 12
42#define WL1273_MOST_BLEND_SET 13
43#define WL1273_DEMPH_MODE_SET 14
44#define WL1273_SEARCH_LVL_SET 15
45#define WL1273_BAND_SET 16
46#define WL1273_MUTE_STATUS_SET 17
47#define WL1273_RDS_PAUSE_LVL_SET 18
48#define WL1273_RDS_PAUSE_DUR_SET 19
49#define WL1273_RDS_MEM_SET 20
50#define WL1273_RDS_BLK_B_SET 21
51#define WL1273_RDS_MSK_B_SET 22
52#define WL1273_RDS_PI_MASK_SET 23
53#define WL1273_RDS_PI_SET 24
54#define WL1273_RDS_SYSTEM_SET 25
55#define WL1273_INT_MASK_SET 26
56#define WL1273_SEARCH_DIR_SET 27
57#define WL1273_VOLUME_SET 28
58#define WL1273_AUDIO_ENABLE 29
59#define WL1273_PCM_MODE_SET 30
60#define WL1273_I2S_MODE_CONFIG_SET 31
61#define WL1273_POWER_SET 32
62#define WL1273_INTX_CONFIG_SET 33
63#define WL1273_PULL_EN_SET 34
64#define WL1273_HILO_SET 35
65#define WL1273_SWITCH2FREF 36
66#define WL1273_FREQ_DRIFT_REPORT 37
67
68#define WL1273_PCE_GET 40
69#define WL1273_FIRM_VER_GET 41
70#define WL1273_ASIC_VER_GET 42
71#define WL1273_ASIC_ID_GET 43
72#define WL1273_MAN_ID_GET 44
73#define WL1273_TUNER_MODE_SET 45
74#define WL1273_STOP_SEARCH 46
75#define WL1273_RDS_CNTRL_SET 47
76
77#define WL1273_WRITE_HARDWARE_REG 100
78#define WL1273_CODE_DOWNLOAD 101
79#define WL1273_RESET 102
80
81#define WL1273_FM_POWER_MODE 254
82#define WL1273_FM_INTERRUPT 255
83
84/* Transmitter API */
85
86#define WL1273_CHANL_SET 55
87#define WL1273_SCAN_SPACING_SET 56
88#define WL1273_REF_SET 57
89#define WL1273_POWER_ENB_SET 90
90#define WL1273_POWER_ATT_SET 58
91#define WL1273_POWER_LEV_SET 59
92#define WL1273_AUDIO_DEV_SET 60
93#define WL1273_PILOT_DEV_SET 61
94#define WL1273_RDS_DEV_SET 62
95#define WL1273_PUPD_SET 91
96#define WL1273_AUDIO_IO_SET 63
97#define WL1273_PREMPH_SET 64
98#define WL1273_MONO_SET 66
99#define WL1273_MUTE 92
100#define WL1273_MPX_LMT_ENABLE 67
101#define WL1273_PI_SET 93
102#define WL1273_ECC_SET 69
103#define WL1273_PTY 70
104#define WL1273_AF 71
105#define WL1273_DISPLAY_MODE 74
106#define WL1273_RDS_REP_SET 77
107#define WL1273_RDS_CONFIG_DATA_SET 98
108#define WL1273_RDS_DATA_SET 99
109#define WL1273_RDS_DATA_ENB 94
110#define WL1273_TA_SET 78
111#define WL1273_TP_SET 79
112#define WL1273_DI_SET 80
113#define WL1273_MS_SET 81
114#define WL1273_PS_SCROLL_SPEED 82
115#define WL1273_TX_AUDIO_LEVEL_TEST 96
116#define WL1273_TX_AUDIO_LEVEL_TEST_THRESHOLD 73
117#define WL1273_TX_AUDIO_INPUT_LEVEL_RANGE_SET 54
118#define WL1273_RX_ANTENNA_SELECT 87
119#define WL1273_I2C_DEV_ADDR_SET 86
120#define WL1273_REF_ERR_CALIB_PARAM_SET 88
121#define WL1273_REF_ERR_CALIB_PERIODICITY_SET 89
122#define WL1273_SOC_INT_TRIGGER 52
123#define WL1273_SOC_AUDIO_PATH_SET 83
124#define WL1273_SOC_PCMI_OVERRIDE 84
125#define WL1273_SOC_I2S_OVERRIDE 85
126#define WL1273_RSSI_BLOCK_SCAN_FREQ_SET 95
127#define WL1273_RSSI_BLOCK_SCAN_START 97
128#define WL1273_RSSI_BLOCK_SCAN_DATA_GET 5
129#define WL1273_READ_FMANT_TUNE_VALUE 104
130
131#define WL1273_RDS_OFF 0
132#define WL1273_RDS_ON 1
133#define WL1273_RDS_RESET 2
134
135#define WL1273_AUDIO_DIGITAL 0
136#define WL1273_AUDIO_ANALOG 1
137
138#define WL1273_MODE_RX BIT(0)
139#define WL1273_MODE_TX BIT(1)
140#define WL1273_MODE_OFF BIT(2)
141#define WL1273_MODE_SUSPENDED BIT(3)
142
143#define WL1273_RADIO_CHILD BIT(0)
144#define WL1273_CODEC_CHILD BIT(1)
145
146#define WL1273_RX_MONO 1
147#define WL1273_RX_STEREO 0
148#define WL1273_TX_MONO 0
149#define WL1273_TX_STEREO 1
150
151#define WL1273_MAX_VOLUME 0xffff
152#define WL1273_DEFAULT_VOLUME 0x78b8
153
154/* I2S protocol, left channel first, data width 16 bits */
155#define WL1273_PCM_DEF_MODE 0x00
156
157/* Rx */
158#define WL1273_AUDIO_ENABLE_I2S BIT(0)
159#define WL1273_AUDIO_ENABLE_ANALOG BIT(1)
160
161/* Tx */
162#define WL1273_AUDIO_IO_SET_ANALOG 0
163#define WL1273_AUDIO_IO_SET_I2S 1
164
165#define WL1273_PUPD_SET_OFF 0x00
166#define WL1273_PUPD_SET_ON 0x01
167#define WL1273_PUPD_SET_RETENTION 0x10
168
169/* I2S mode */
170#define WL1273_IS2_WIDTH_32 0x0
171#define WL1273_IS2_WIDTH_40 0x1
172#define WL1273_IS2_WIDTH_22_23 0x2
173#define WL1273_IS2_WIDTH_23_22 0x3
174#define WL1273_IS2_WIDTH_48 0x4
175#define WL1273_IS2_WIDTH_50 0x5
176#define WL1273_IS2_WIDTH_60 0x6
177#define WL1273_IS2_WIDTH_64 0x7
178#define WL1273_IS2_WIDTH_80 0x8
179#define WL1273_IS2_WIDTH_96 0x9
180#define WL1273_IS2_WIDTH_128 0xa
181#define WL1273_IS2_WIDTH 0xf
182
183#define WL1273_IS2_FORMAT_STD (0x0 << 4)
184#define WL1273_IS2_FORMAT_LEFT (0x1 << 4)
185#define WL1273_IS2_FORMAT_RIGHT (0x2 << 4)
186#define WL1273_IS2_FORMAT_USER (0x3 << 4)
187
188#define WL1273_IS2_MASTER (0x0 << 6)
189#define WL1273_IS2_SLAVEW (0x1 << 6)
190
191#define WL1273_IS2_TRI_AFTER_SENDING (0x0 << 7)
192#define WL1273_IS2_TRI_ALWAYS_ACTIVE (0x1 << 7)
193
194#define WL1273_IS2_SDOWS_RR (0x0 << 8)
195#define WL1273_IS2_SDOWS_RF (0x1 << 8)
196#define WL1273_IS2_SDOWS_FR (0x2 << 8)
197#define WL1273_IS2_SDOWS_FF (0x3 << 8)
198
199#define WL1273_IS2_TRI_OPT (0x0 << 10)
200#define WL1273_IS2_TRI_ALWAYS (0x1 << 10)
201
202#define WL1273_IS2_RATE_48K (0x0 << 12)
203#define WL1273_IS2_RATE_44_1K (0x1 << 12)
204#define WL1273_IS2_RATE_32K (0x2 << 12)
205#define WL1273_IS2_RATE_22_05K (0x4 << 12)
206#define WL1273_IS2_RATE_16K (0x5 << 12)
207#define WL1273_IS2_RATE_12K (0x8 << 12)
208#define WL1273_IS2_RATE_11_025 (0x9 << 12)
209#define WL1273_IS2_RATE_8K (0xa << 12)
210#define WL1273_IS2_RATE (0xf << 12)
211
212#define WL1273_I2S_DEF_MODE (WL1273_IS2_WIDTH_32 | \
213 WL1273_IS2_FORMAT_STD | \
214 WL1273_IS2_MASTER | \
215 WL1273_IS2_TRI_AFTER_SENDING | \
216 WL1273_IS2_SDOWS_RR | \
217 WL1273_IS2_TRI_OPT | \
218 WL1273_IS2_RATE_48K)
219
220#define SCHAR_MIN (-128)
221#define SCHAR_MAX 127
222
223#define WL1273_FR_EVENT BIT(0)
224#define WL1273_BL_EVENT BIT(1)
225#define WL1273_RDS_EVENT BIT(2)
226#define WL1273_BBLK_EVENT BIT(3)
227#define WL1273_LSYNC_EVENT BIT(4)
228#define WL1273_LEV_EVENT BIT(5)
229#define WL1273_IFFR_EVENT BIT(6)
230#define WL1273_PI_EVENT BIT(7)
231#define WL1273_PD_EVENT BIT(8)
232#define WL1273_STIC_EVENT BIT(9)
233#define WL1273_MAL_EVENT BIT(10)
234#define WL1273_POW_ENB_EVENT BIT(11)
235#define WL1273_SCAN_OVER_EVENT BIT(12)
236#define WL1273_ERROR_EVENT BIT(13)
237
238#define TUNER_MODE_STOP_SEARCH 0
239#define TUNER_MODE_PRESET 1
240#define TUNER_MODE_AUTO_SEEK 2
241#define TUNER_MODE_AF 3
242#define TUNER_MODE_AUTO_SEEK_PI 4
243#define TUNER_MODE_AUTO_SEEK_BULK 5
244
245#define RDS_BLOCK_SIZE 3
246
247struct wl1273_fm_platform_data {
248 int (*request_resources) (struct i2c_client *client);
249 void (*free_resources) (void);
250 void (*enable) (void);
251 void (*disable) (void);
252
253 u8 forbidden_modes;
254 unsigned int children;
255};
256
257#define WL1273_FM_CORE_CELLS 2
258
259#define WL1273_BAND_OTHER 0
260#define WL1273_BAND_JAPAN 1
261
262#define WL1273_BAND_JAPAN_LOW 76000
263#define WL1273_BAND_JAPAN_HIGH 90000
264#define WL1273_BAND_OTHER_LOW 87500
265#define WL1273_BAND_OTHER_HIGH 108000
266
267#define WL1273_BAND_TX_LOW 76000
268#define WL1273_BAND_TX_HIGH 108000
269
270struct wl1273_core {
271 struct mfd_cell cells[WL1273_FM_CORE_CELLS];
272 struct wl1273_fm_platform_data *pdata;
273
274 unsigned int mode;
275 unsigned int i2s_mode;
276 unsigned int volume;
277 unsigned int audio_mode;
278 unsigned int channel_number;
279 struct mutex lock; /* for serializing fm radio operations */
280
281 struct i2c_client *client;
282
283 int (*write)(struct wl1273_core *core, u8, u16);
284 int (*set_audio)(struct wl1273_core *core, unsigned int);
285 int (*set_volume)(struct wl1273_core *core, unsigned int);
286};
287
288#endif /* ifndef WL1273_CORE_H */
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index a1239c48b41a..903280d21866 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -245,6 +245,7 @@ enum wm831x_parent {
245 WM8320 = 0x8320, 245 WM8320 = 0x8320,
246 WM8321 = 0x8321, 246 WM8321 = 0x8321,
247 WM8325 = 0x8325, 247 WM8325 = 0x8325,
248 WM8326 = 0x8326,
248}; 249};
249 250
250struct wm831x { 251struct wm831x {
diff --git a/include/linux/mfd/wm8350/audio.h b/include/linux/mfd/wm8350/audio.h
index a95141eafce3..bd581c6fa085 100644
--- a/include/linux/mfd/wm8350/audio.h
+++ b/include/linux/mfd/wm8350/audio.h
@@ -522,9 +522,6 @@
522#define WM8350_MCLK_SEL_PLL_32K 3 522#define WM8350_MCLK_SEL_PLL_32K 3
523#define WM8350_MCLK_SEL_MCLK 5 523#define WM8350_MCLK_SEL_MCLK 5
524 524
525#define WM8350_MCLK_DIR_OUT 0
526#define WM8350_MCLK_DIR_IN 1
527
528/* clock divider id's */ 525/* clock divider id's */
529#define WM8350_ADC_CLKDIV 0 526#define WM8350_ADC_CLKDIV 0
530#define WM8350_DAC_CLKDIV 1 527#define WM8350_DAC_CLKDIV 1
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index de79baee4925..3fd36845ca45 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -17,6 +17,11 @@
17 17
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19 19
20enum wm8994_type {
21 WM8994 = 0,
22 WM8958 = 1,
23};
24
20struct regulator_dev; 25struct regulator_dev;
21struct regulator_bulk_data; 26struct regulator_bulk_data;
22 27
@@ -48,6 +53,8 @@ struct wm8994 {
48 struct mutex io_lock; 53 struct mutex io_lock;
49 struct mutex irq_lock; 54 struct mutex irq_lock;
50 55
56 enum wm8994_type type;
57
51 struct device *dev; 58 struct device *dev;
52 int (*read_dev)(struct wm8994 *wm8994, unsigned short reg, 59 int (*read_dev)(struct wm8994 *wm8994, unsigned short reg,
53 int bytes, void *dest); 60 int bytes, void *dest);
@@ -68,6 +75,7 @@ struct wm8994 {
68 u16 gpio_regs[WM8994_NUM_GPIO_REGS]; 75 u16 gpio_regs[WM8994_NUM_GPIO_REGS];
69 76
70 struct regulator_dev *dbvdd; 77 struct regulator_dev *dbvdd;
78 int num_supplies;
71 struct regulator_bulk_data *supplies; 79 struct regulator_bulk_data *supplies;
72}; 80};
73 81
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index 5c51f367c061..9eab263658be 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -29,7 +29,9 @@ struct wm8994_ldo_pdata {
29#define WM8994_CONFIGURE_GPIO 0x8000 29#define WM8994_CONFIGURE_GPIO 0x8000
30 30
31#define WM8994_DRC_REGS 5 31#define WM8994_DRC_REGS 5
32#define WM8994_EQ_REGS 19 32#define WM8994_EQ_REGS 20
33#define WM8958_MBC_CUTOFF_REGS 20
34#define WM8958_MBC_COEFF_REGS 48
33 35
34/** 36/**
35 * DRC configurations are specified with a label and a set of register 37 * DRC configurations are specified with a label and a set of register
@@ -59,6 +61,18 @@ struct wm8994_retune_mobile_cfg {
59 u16 regs[WM8994_EQ_REGS]; 61 u16 regs[WM8994_EQ_REGS];
60}; 62};
61 63
64/**
65 * Multiband compressor configurations are specified with a label and
66 * two sets of values to write. Configurations are expected to be
67 * generated using the multiband compressor configuration panel in
68 * WISCE - see http://www.wolfsonmicro.com/wisce/
69 */
70struct wm8958_mbc_cfg {
71 const char *name;
72 u16 cutoff_regs[WM8958_MBC_CUTOFF_REGS];
73 u16 coeff_regs[WM8958_MBC_COEFF_REGS];
74};
75
62struct wm8994_pdata { 76struct wm8994_pdata {
63 int gpio_base; 77 int gpio_base;
64 78
@@ -78,6 +92,9 @@ struct wm8994_pdata {
78 int num_retune_mobile_cfgs; 92 int num_retune_mobile_cfgs;
79 struct wm8994_retune_mobile_cfg *retune_mobile_cfgs; 93 struct wm8994_retune_mobile_cfg *retune_mobile_cfgs;
80 94
95 int num_mbc_cfgs;
96 struct wm8958_mbc_cfg *mbc_cfgs;
97
81 /* LINEOUT can be differential or single ended */ 98 /* LINEOUT can be differential or single ended */
82 unsigned int lineout1_diff:1; 99 unsigned int lineout1_diff:1;
83 unsigned int lineout2_diff:1; 100 unsigned int lineout2_diff:1;
diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h
index 967f62f54159..be072faec6f0 100644
--- a/include/linux/mfd/wm8994/registers.h
+++ b/include/linux/mfd/wm8994/registers.h
@@ -64,12 +64,16 @@
64#define WM8994_LDO_1 0x3B 64#define WM8994_LDO_1 0x3B
65#define WM8994_LDO_2 0x3C 65#define WM8994_LDO_2 0x3C
66#define WM8994_CHARGE_PUMP_1 0x4C 66#define WM8994_CHARGE_PUMP_1 0x4C
67#define WM8958_CHARGE_PUMP_2 0x4D
67#define WM8994_CLASS_W_1 0x51 68#define WM8994_CLASS_W_1 0x51
68#define WM8994_DC_SERVO_1 0x54 69#define WM8994_DC_SERVO_1 0x54
69#define WM8994_DC_SERVO_2 0x55 70#define WM8994_DC_SERVO_2 0x55
70#define WM8994_DC_SERVO_4 0x57 71#define WM8994_DC_SERVO_4 0x57
71#define WM8994_DC_SERVO_READBACK 0x58 72#define WM8994_DC_SERVO_READBACK 0x58
72#define WM8994_ANALOGUE_HP_1 0x60 73#define WM8994_ANALOGUE_HP_1 0x60
74#define WM8958_MIC_DETECT_1 0xD0
75#define WM8958_MIC_DETECT_2 0xD1
76#define WM8958_MIC_DETECT_3 0xD2
73#define WM8994_CHIP_REVISION 0x100 77#define WM8994_CHIP_REVISION 0x100
74#define WM8994_CONTROL_INTERFACE 0x101 78#define WM8994_CONTROL_INTERFACE 0x101
75#define WM8994_WRITE_SEQUENCER_CTRL_1 0x110 79#define WM8994_WRITE_SEQUENCER_CTRL_1 0x110
@@ -109,6 +113,10 @@
109#define WM8994_AIF2DAC_LRCLK 0x315 113#define WM8994_AIF2DAC_LRCLK 0x315
110#define WM8994_AIF2DAC_DATA 0x316 114#define WM8994_AIF2DAC_DATA 0x316
111#define WM8994_AIF2ADC_DATA 0x317 115#define WM8994_AIF2ADC_DATA 0x317
116#define WM8958_AIF3_CONTROL_1 0x320
117#define WM8958_AIF3_CONTROL_2 0x321
118#define WM8958_AIF3DAC_DATA 0x322
119#define WM8958_AIF3ADC_DATA 0x323
112#define WM8994_AIF1_ADC1_LEFT_VOLUME 0x400 120#define WM8994_AIF1_ADC1_LEFT_VOLUME 0x400
113#define WM8994_AIF1_ADC1_RIGHT_VOLUME 0x401 121#define WM8994_AIF1_ADC1_RIGHT_VOLUME 0x401
114#define WM8994_AIF1_DAC1_LEFT_VOLUME 0x402 122#define WM8994_AIF1_DAC1_LEFT_VOLUME 0x402
@@ -242,6 +250,83 @@
242#define WM8994_INTERRUPT_STATUS_2_MASK 0x739 250#define WM8994_INTERRUPT_STATUS_2_MASK 0x739
243#define WM8994_INTERRUPT_CONTROL 0x740 251#define WM8994_INTERRUPT_CONTROL 0x740
244#define WM8994_IRQ_DEBOUNCE 0x748 252#define WM8994_IRQ_DEBOUNCE 0x748
253#define WM8958_DSP2_PROGRAM 0x900
254#define WM8958_DSP2_CONFIG 0x901
255#define WM8958_DSP2_MAGICNUM 0xA00
256#define WM8958_DSP2_RELEASEYEAR 0xA01
257#define WM8958_DSP2_RELEASEMONTHDAY 0xA02
258#define WM8958_DSP2_RELEASETIME 0xA03
259#define WM8958_DSP2_VERMAJMIN 0xA04
260#define WM8958_DSP2_VERBUILD 0xA05
261#define WM8958_DSP2_EXECCONTROL 0xA0D
262#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1 0x2200
263#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2 0x2201
264#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1 0x2202
265#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_2 0x2203
266#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_1 0x2204
267#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_2 0x2205
268#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_1 0x2206
269#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_2 0x2207
270#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_1 0x2208
271#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_2 0x2209
272#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_1 0x220A
273#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_2 0x220B
274#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_1 0x220C
275#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_2 0x220D
276#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_1 0x220E
277#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_2 0x220F
278#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_1 0x2210
279#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_2 0x2211
280#define WM8958_MBC_BAND_1_LOWER_CUTOFF_1 0x2212
281#define WM8958_MBC_BAND_1_LOWER_CUTOFF_2 0x2213
282#define WM8958_MBC_BAND_1_K_1 0x2400
283#define WM8958_MBC_BAND_1_K_2 0x2401
284#define WM8958_MBC_BAND_1_N1_1 0x2402
285#define WM8958_MBC_BAND_1_N1_2 0x2403
286#define WM8958_MBC_BAND_1_N2_1 0x2404
287#define WM8958_MBC_BAND_1_N2_2 0x2405
288#define WM8958_MBC_BAND_1_N3_1 0x2406
289#define WM8958_MBC_BAND_1_N3_2 0x2407
290#define WM8958_MBC_BAND_1_N4_1 0x2408
291#define WM8958_MBC_BAND_1_N4_2 0x2409
292#define WM8958_MBC_BAND_1_N5_1 0x240A
293#define WM8958_MBC_BAND_1_N5_2 0x240B
294#define WM8958_MBC_BAND_1_X1_1 0x240C
295#define WM8958_MBC_BAND_1_X1_2 0x240D
296#define WM8958_MBC_BAND_1_X2_1 0x240E
297#define WM8958_MBC_BAND_1_X2_2 0x240F
298#define WM8958_MBC_BAND_1_X3_1 0x2410
299#define WM8958_MBC_BAND_1_X3_2 0x2411
300#define WM8958_MBC_BAND_1_ATTACK_1 0x2412
301#define WM8958_MBC_BAND_1_ATTACK_2 0x2413
302#define WM8958_MBC_BAND_1_DECAY_1 0x2414
303#define WM8958_MBC_BAND_1_DECAY_2 0x2415
304#define WM8958_MBC_BAND_2_K_1 0x2416
305#define WM8958_MBC_BAND_2_K_2 0x2417
306#define WM8958_MBC_BAND_2_N1_1 0x2418
307#define WM8958_MBC_BAND_2_N1_2 0x2419
308#define WM8958_MBC_BAND_2_N2_1 0x241A
309#define WM8958_MBC_BAND_2_N2_2 0x241B
310#define WM8958_MBC_BAND_2_N3_1 0x241C
311#define WM8958_MBC_BAND_2_N3_2 0x241D
312#define WM8958_MBC_BAND_2_N4_1 0x241E
313#define WM8958_MBC_BAND_2_N4_2 0x241F
314#define WM8958_MBC_BAND_2_N5_1 0x2420
315#define WM8958_MBC_BAND_2_N5_2 0x2421
316#define WM8958_MBC_BAND_2_X1_1 0x2422
317#define WM8958_MBC_BAND_2_X1_2 0x2423
318#define WM8958_MBC_BAND_2_X2_1 0x2424
319#define WM8958_MBC_BAND_2_X2_2 0x2425
320#define WM8958_MBC_BAND_2_X3_1 0x2426
321#define WM8958_MBC_BAND_2_X3_2 0x2427
322#define WM8958_MBC_BAND_2_ATTACK_1 0x2428
323#define WM8958_MBC_BAND_2_ATTACK_2 0x2429
324#define WM8958_MBC_BAND_2_DECAY_1 0x242A
325#define WM8958_MBC_BAND_2_DECAY_2 0x242B
326#define WM8958_MBC_B2_PG2_1 0x242C
327#define WM8958_MBC_B2_PG2_2 0x242D
328#define WM8958_MBC_B1_PG2_1 0x242E
329#define WM8958_MBC_B1_PG2_2 0x242F
245#define WM8994_WRITE_SEQUENCER_0 0x3000 330#define WM8994_WRITE_SEQUENCER_0 0x3000
246#define WM8994_WRITE_SEQUENCER_1 0x3001 331#define WM8994_WRITE_SEQUENCER_1 0x3001
247#define WM8994_WRITE_SEQUENCER_2 0x3002 332#define WM8994_WRITE_SEQUENCER_2 0x3002
@@ -992,6 +1077,12 @@
992/* 1077/*
993 * R6 (0x06) - Power Management (6) 1078 * R6 (0x06) - Power Management (6)
994 */ 1079 */
1080#define WM8958_AIF3ADC_SRC_MASK 0x0600 /* AIF3ADC_SRC - [10:9] */
1081#define WM8958_AIF3ADC_SRC_SHIFT 9 /* AIF3ADC_SRC - [10:9] */
1082#define WM8958_AIF3ADC_SRC_WIDTH 2 /* AIF3ADC_SRC - [10:9] */
1083#define WM8958_AIF2DAC_SRC_MASK 0x0180 /* AIF2DAC_SRC - [8:7] */
1084#define WM8958_AIF2DAC_SRC_SHIFT 7 /* AIF2DAC_SRC - [8:7] */
1085#define WM8958_AIF2DAC_SRC_WIDTH 2 /* AIF2DAC_SRC - [8:7] */
995#define WM8994_AIF3_TRI 0x0020 /* AIF3_TRI */ 1086#define WM8994_AIF3_TRI 0x0020 /* AIF3_TRI */
996#define WM8994_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */ 1087#define WM8994_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */
997#define WM8994_AIF3_TRI_SHIFT 5 /* AIF3_TRI */ 1088#define WM8994_AIF3_TRI_SHIFT 5 /* AIF3_TRI */
@@ -1836,6 +1927,14 @@
1836#define WM8994_CP_ENA_WIDTH 1 /* CP_ENA */ 1927#define WM8994_CP_ENA_WIDTH 1 /* CP_ENA */
1837 1928
1838/* 1929/*
1930 * R77 (0x4D) - Charge Pump (2)
1931 */
1932#define WM8958_CP_DISCH 0x8000 /* CP_DISCH */
1933#define WM8958_CP_DISCH_MASK 0x8000 /* CP_DISCH */
1934#define WM8958_CP_DISCH_SHIFT 15 /* CP_DISCH */
1935#define WM8958_CP_DISCH_WIDTH 1 /* CP_DISCH */
1936
1937/*
1839 * R81 (0x51) - Class W (1) 1938 * R81 (0x51) - Class W (1)
1840 */ 1939 */
1841#define WM8994_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */ 1940#define WM8994_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */
@@ -1952,6 +2051,46 @@
1952#define WM8994_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ 2051#define WM8994_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
1953 2052
1954/* 2053/*
2054 * R208 (0xD0) - Mic Detect 1
2055 */
2056#define WM8958_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */
2057#define WM8958_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */
2058#define WM8958_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */
2059#define WM8958_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */
2060#define WM8958_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */
2061#define WM8958_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */
2062#define WM8958_MICD_DBTIME 0x0002 /* MICD_DBTIME */
2063#define WM8958_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */
2064#define WM8958_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
2065#define WM8958_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
2066#define WM8958_MICD_ENA 0x0001 /* MICD_ENA */
2067#define WM8958_MICD_ENA_MASK 0x0001 /* MICD_ENA */
2068#define WM8958_MICD_ENA_SHIFT 0 /* MICD_ENA */
2069#define WM8958_MICD_ENA_WIDTH 1 /* MICD_ENA */
2070
2071/*
2072 * R209 (0xD1) - Mic Detect 2
2073 */
2074#define WM8958_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */
2075#define WM8958_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */
2076#define WM8958_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */
2077
2078/*
2079 * R210 (0xD2) - Mic Detect 3
2080 */
2081#define WM8958_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */
2082#define WM8958_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */
2083#define WM8958_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */
2084#define WM8958_MICD_VALID 0x0002 /* MICD_VALID */
2085#define WM8958_MICD_VALID_MASK 0x0002 /* MICD_VALID */
2086#define WM8958_MICD_VALID_SHIFT 1 /* MICD_VALID */
2087#define WM8958_MICD_VALID_WIDTH 1 /* MICD_VALID */
2088#define WM8958_MICD_STS 0x0001 /* MICD_STS */
2089#define WM8958_MICD_STS_MASK 0x0001 /* MICD_STS */
2090#define WM8958_MICD_STS_SHIFT 0 /* MICD_STS */
2091#define WM8958_MICD_STS_WIDTH 1 /* MICD_STS */
2092
2093/*
1955 * R256 (0x100) - Chip Revision 2094 * R256 (0x100) - Chip Revision
1956 */ 2095 */
1957#define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 2096#define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */
@@ -2069,6 +2208,14 @@
2069/* 2208/*
2070 * R520 (0x208) - Clocking (1) 2209 * R520 (0x208) - Clocking (1)
2071 */ 2210 */
2211#define WM8958_DSP2CLK_ENA 0x4000 /* DSP2CLK_ENA */
2212#define WM8958_DSP2CLK_ENA_MASK 0x4000 /* DSP2CLK_ENA */
2213#define WM8958_DSP2CLK_ENA_SHIFT 14 /* DSP2CLK_ENA */
2214#define WM8958_DSP2CLK_ENA_WIDTH 1 /* DSP2CLK_ENA */
2215#define WM8958_DSP2CLK_SRC 0x1000 /* DSP2CLK_SRC */
2216#define WM8958_DSP2CLK_SRC_MASK 0x1000 /* DSP2CLK_SRC */
2217#define WM8958_DSP2CLK_SRC_SHIFT 12 /* DSP2CLK_SRC */
2218#define WM8958_DSP2CLK_SRC_WIDTH 1 /* DSP2CLK_SRC */
2072#define WM8994_TOCLK_ENA 0x0010 /* TOCLK_ENA */ 2219#define WM8994_TOCLK_ENA 0x0010 /* TOCLK_ENA */
2073#define WM8994_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ 2220#define WM8994_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */
2074#define WM8994_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ 2221#define WM8994_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */
@@ -2553,6 +2700,63 @@
2553#define WM8994_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */ 2700#define WM8994_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */
2554 2701
2555/* 2702/*
2703 * R800 (0x320) - AIF3 Control (1)
2704 */
2705#define WM8958_AIF3_LRCLK_INV 0x0080 /* AIF3_LRCLK_INV */
2706#define WM8958_AIF3_LRCLK_INV_MASK 0x0080 /* AIF3_LRCLK_INV */
2707#define WM8958_AIF3_LRCLK_INV_SHIFT 7 /* AIF3_LRCLK_INV */
2708#define WM8958_AIF3_LRCLK_INV_WIDTH 1 /* AIF3_LRCLK_INV */
2709#define WM8958_AIF3_WL_MASK 0x0060 /* AIF3_WL - [6:5] */
2710#define WM8958_AIF3_WL_SHIFT 5 /* AIF3_WL - [6:5] */
2711#define WM8958_AIF3_WL_WIDTH 2 /* AIF3_WL - [6:5] */
2712#define WM8958_AIF3_FMT_MASK 0x0018 /* AIF3_FMT - [4:3] */
2713#define WM8958_AIF3_FMT_SHIFT 3 /* AIF3_FMT - [4:3] */
2714#define WM8958_AIF3_FMT_WIDTH 2 /* AIF3_FMT - [4:3] */
2715
2716/*
2717 * R801 (0x321) - AIF3 Control (2)
2718 */
2719#define WM8958_AIF3DAC_BOOST_MASK 0x0C00 /* AIF3DAC_BOOST - [11:10] */
2720#define WM8958_AIF3DAC_BOOST_SHIFT 10 /* AIF3DAC_BOOST - [11:10] */
2721#define WM8958_AIF3DAC_BOOST_WIDTH 2 /* AIF3DAC_BOOST - [11:10] */
2722#define WM8958_AIF3DAC_COMP 0x0010 /* AIF3DAC_COMP */
2723#define WM8958_AIF3DAC_COMP_MASK 0x0010 /* AIF3DAC_COMP */
2724#define WM8958_AIF3DAC_COMP_SHIFT 4 /* AIF3DAC_COMP */
2725#define WM8958_AIF3DAC_COMP_WIDTH 1 /* AIF3DAC_COMP */
2726#define WM8958_AIF3DAC_COMPMODE 0x0008 /* AIF3DAC_COMPMODE */
2727#define WM8958_AIF3DAC_COMPMODE_MASK 0x0008 /* AIF3DAC_COMPMODE */
2728#define WM8958_AIF3DAC_COMPMODE_SHIFT 3 /* AIF3DAC_COMPMODE */
2729#define WM8958_AIF3DAC_COMPMODE_WIDTH 1 /* AIF3DAC_COMPMODE */
2730#define WM8958_AIF3ADC_COMP 0x0004 /* AIF3ADC_COMP */
2731#define WM8958_AIF3ADC_COMP_MASK 0x0004 /* AIF3ADC_COMP */
2732#define WM8958_AIF3ADC_COMP_SHIFT 2 /* AIF3ADC_COMP */
2733#define WM8958_AIF3ADC_COMP_WIDTH 1 /* AIF3ADC_COMP */
2734#define WM8958_AIF3ADC_COMPMODE 0x0002 /* AIF3ADC_COMPMODE */
2735#define WM8958_AIF3ADC_COMPMODE_MASK 0x0002 /* AIF3ADC_COMPMODE */
2736#define WM8958_AIF3ADC_COMPMODE_SHIFT 1 /* AIF3ADC_COMPMODE */
2737#define WM8958_AIF3ADC_COMPMODE_WIDTH 1 /* AIF3ADC_COMPMODE */
2738#define WM8958_AIF3_LOOPBACK 0x0001 /* AIF3_LOOPBACK */
2739#define WM8958_AIF3_LOOPBACK_MASK 0x0001 /* AIF3_LOOPBACK */
2740#define WM8958_AIF3_LOOPBACK_SHIFT 0 /* AIF3_LOOPBACK */
2741#define WM8958_AIF3_LOOPBACK_WIDTH 1 /* AIF3_LOOPBACK */
2742
2743/*
2744 * R802 (0x322) - AIF3DAC Data
2745 */
2746#define WM8958_AIF3DAC_DAT_INV 0x0001 /* AIF3DAC_DAT_INV */
2747#define WM8958_AIF3DAC_DAT_INV_MASK 0x0001 /* AIF3DAC_DAT_INV */
2748#define WM8958_AIF3DAC_DAT_INV_SHIFT 0 /* AIF3DAC_DAT_INV */
2749#define WM8958_AIF3DAC_DAT_INV_WIDTH 1 /* AIF3DAC_DAT_INV */
2750
2751/*
2752 * R803 (0x323) - AIF3ADC Data
2753 */
2754#define WM8958_AIF3ADC_DAT_INV 0x0001 /* AIF3ADC_DAT_INV */
2755#define WM8958_AIF3ADC_DAT_INV_MASK 0x0001 /* AIF3ADC_DAT_INV */
2756#define WM8958_AIF3ADC_DAT_INV_SHIFT 0 /* AIF3ADC_DAT_INV */
2757#define WM8958_AIF3ADC_DAT_INV_WIDTH 1 /* AIF3ADC_DAT_INV */
2758
2759/*
2556 * R1024 (0x400) - AIF1 ADC1 Left Volume 2760 * R1024 (0x400) - AIF1 ADC1 Left Volume
2557 */ 2761 */
2558#define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 2762#define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
@@ -4289,4 +4493,102 @@
4289#define WM8994_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */ 4493#define WM8994_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */
4290#define WM8994_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */ 4494#define WM8994_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */
4291 4495
4496/*
4497 * R2304 (0x900) - DSP2_Program
4498 */
4499#define WM8958_DSP2_ENA 0x0001 /* DSP2_ENA */
4500#define WM8958_DSP2_ENA_MASK 0x0001 /* DSP2_ENA */
4501#define WM8958_DSP2_ENA_SHIFT 0 /* DSP2_ENA */
4502#define WM8958_DSP2_ENA_WIDTH 1 /* DSP2_ENA */
4503
4504/*
4505 * R2305 (0x901) - DSP2_Config
4506 */
4507#define WM8958_MBC_SEL_MASK 0x0030 /* MBC_SEL - [5:4] */
4508#define WM8958_MBC_SEL_SHIFT 4 /* MBC_SEL - [5:4] */
4509#define WM8958_MBC_SEL_WIDTH 2 /* MBC_SEL - [5:4] */
4510#define WM8958_MBC_ENA 0x0001 /* MBC_ENA */
4511#define WM8958_MBC_ENA_MASK 0x0001 /* MBC_ENA */
4512#define WM8958_MBC_ENA_SHIFT 0 /* MBC_ENA */
4513#define WM8958_MBC_ENA_WIDTH 1 /* MBC_ENA */
4514
4515/*
4516 * R2560 (0xA00) - DSP2_MagicNum
4517 */
4518#define WM8958_DSP2_MAGIC_NUM_MASK 0xFFFF /* DSP2_MAGIC_NUM - [15:0] */
4519#define WM8958_DSP2_MAGIC_NUM_SHIFT 0 /* DSP2_MAGIC_NUM - [15:0] */
4520#define WM8958_DSP2_MAGIC_NUM_WIDTH 16 /* DSP2_MAGIC_NUM - [15:0] */
4521
4522/*
4523 * R2561 (0xA01) - DSP2_ReleaseYear
4524 */
4525#define WM8958_DSP2_RELEASE_YEAR_MASK 0xFFFF /* DSP2_RELEASE_YEAR - [15:0] */
4526#define WM8958_DSP2_RELEASE_YEAR_SHIFT 0 /* DSP2_RELEASE_YEAR - [15:0] */
4527#define WM8958_DSP2_RELEASE_YEAR_WIDTH 16 /* DSP2_RELEASE_YEAR - [15:0] */
4528
4529/*
4530 * R2562 (0xA02) - DSP2_ReleaseMonthDay
4531 */
4532#define WM8958_DSP2_RELEASE_MONTH_MASK 0xFF00 /* DSP2_RELEASE_MONTH - [15:8] */
4533#define WM8958_DSP2_RELEASE_MONTH_SHIFT 8 /* DSP2_RELEASE_MONTH - [15:8] */
4534#define WM8958_DSP2_RELEASE_MONTH_WIDTH 8 /* DSP2_RELEASE_MONTH - [15:8] */
4535#define WM8958_DSP2_RELEASE_DAY_MASK 0x00FF /* DSP2_RELEASE_DAY - [7:0] */
4536#define WM8958_DSP2_RELEASE_DAY_SHIFT 0 /* DSP2_RELEASE_DAY - [7:0] */
4537#define WM8958_DSP2_RELEASE_DAY_WIDTH 8 /* DSP2_RELEASE_DAY - [7:0] */
4538
4539/*
4540 * R2563 (0xA03) - DSP2_ReleaseTime
4541 */
4542#define WM8958_DSP2_RELEASE_HOURS_MASK 0xFF00 /* DSP2_RELEASE_HOURS - [15:8] */
4543#define WM8958_DSP2_RELEASE_HOURS_SHIFT 8 /* DSP2_RELEASE_HOURS - [15:8] */
4544#define WM8958_DSP2_RELEASE_HOURS_WIDTH 8 /* DSP2_RELEASE_HOURS - [15:8] */
4545#define WM8958_DSP2_RELEASE_MINS_MASK 0x00FF /* DSP2_RELEASE_MINS - [7:0] */
4546#define WM8958_DSP2_RELEASE_MINS_SHIFT 0 /* DSP2_RELEASE_MINS - [7:0] */
4547#define WM8958_DSP2_RELEASE_MINS_WIDTH 8 /* DSP2_RELEASE_MINS - [7:0] */
4548
4549/*
4550 * R2564 (0xA04) - DSP2_VerMajMin
4551 */
4552#define WM8958_DSP2_MAJOR_VER_MASK 0xFF00 /* DSP2_MAJOR_VER - [15:8] */
4553#define WM8958_DSP2_MAJOR_VER_SHIFT 8 /* DSP2_MAJOR_VER - [15:8] */
4554#define WM8958_DSP2_MAJOR_VER_WIDTH 8 /* DSP2_MAJOR_VER - [15:8] */
4555#define WM8958_DSP2_MINOR_VER_MASK 0x00FF /* DSP2_MINOR_VER - [7:0] */
4556#define WM8958_DSP2_MINOR_VER_SHIFT 0 /* DSP2_MINOR_VER - [7:0] */
4557#define WM8958_DSP2_MINOR_VER_WIDTH 8 /* DSP2_MINOR_VER - [7:0] */
4558
4559/*
4560 * R2565 (0xA05) - DSP2_VerBuild
4561 */
4562#define WM8958_DSP2_BUILD_VER_MASK 0xFFFF /* DSP2_BUILD_VER - [15:0] */
4563#define WM8958_DSP2_BUILD_VER_SHIFT 0 /* DSP2_BUILD_VER - [15:0] */
4564#define WM8958_DSP2_BUILD_VER_WIDTH 16 /* DSP2_BUILD_VER - [15:0] */
4565
4566/*
4567 * R2573 (0xA0D) - DSP2_ExecControl
4568 */
4569#define WM8958_DSP2_STOPC 0x0020 /* DSP2_STOPC */
4570#define WM8958_DSP2_STOPC_MASK 0x0020 /* DSP2_STOPC */
4571#define WM8958_DSP2_STOPC_SHIFT 5 /* DSP2_STOPC */
4572#define WM8958_DSP2_STOPC_WIDTH 1 /* DSP2_STOPC */
4573#define WM8958_DSP2_STOPS 0x0010 /* DSP2_STOPS */
4574#define WM8958_DSP2_STOPS_MASK 0x0010 /* DSP2_STOPS */
4575#define WM8958_DSP2_STOPS_SHIFT 4 /* DSP2_STOPS */
4576#define WM8958_DSP2_STOPS_WIDTH 1 /* DSP2_STOPS */
4577#define WM8958_DSP2_STOPI 0x0008 /* DSP2_STOPI */
4578#define WM8958_DSP2_STOPI_MASK 0x0008 /* DSP2_STOPI */
4579#define WM8958_DSP2_STOPI_SHIFT 3 /* DSP2_STOPI */
4580#define WM8958_DSP2_STOPI_WIDTH 1 /* DSP2_STOPI */
4581#define WM8958_DSP2_STOP 0x0004 /* DSP2_STOP */
4582#define WM8958_DSP2_STOP_MASK 0x0004 /* DSP2_STOP */
4583#define WM8958_DSP2_STOP_SHIFT 2 /* DSP2_STOP */
4584#define WM8958_DSP2_STOP_WIDTH 1 /* DSP2_STOP */
4585#define WM8958_DSP2_RUNR 0x0002 /* DSP2_RUNR */
4586#define WM8958_DSP2_RUNR_MASK 0x0002 /* DSP2_RUNR */
4587#define WM8958_DSP2_RUNR_SHIFT 1 /* DSP2_RUNR */
4588#define WM8958_DSP2_RUNR_WIDTH 1 /* DSP2_RUNR */
4589#define WM8958_DSP2_RUN 0x0001 /* DSP2_RUN */
4590#define WM8958_DSP2_RUN_MASK 0x0001 /* DSP2_RUN */
4591#define WM8958_DSP2_RUN_SHIFT 0 /* DSP2_RUN */
4592#define WM8958_DSP2_RUN_WIDTH 1 /* DSP2_RUN */
4593
4292#endif 4594#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 17:06:45 -0500