diff options
author | Jiri Kosina <jkosina@suse.cz> | 2009-12-07 12:36:35 -0500 |
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committer | Jiri Kosina <jkosina@suse.cz> | 2009-12-07 12:36:35 -0500 |
commit | d014d043869cdc591f3a33243d3481fa4479c2d0 (patch) | |
tree | 63626829498e647ba058a1ce06419fe7e4d5f97d /include/linux/mfd | |
parent | 6ec22f9b037fc0c2e00ddb7023fad279c365324d (diff) | |
parent | 6070d81eb5f2d4943223c96e7609a53cdc984364 (diff) |
Merge branch 'for-next' into for-linus
Conflicts:
kernel/irq/chip.c
Diffstat (limited to 'include/linux/mfd')
-rw-r--r-- | include/linux/mfd/ezx-pcap.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h index e5124ceea769..3402042ddc31 100644 --- a/include/linux/mfd/ezx-pcap.h +++ b/include/linux/mfd/ezx-pcap.h | |||
@@ -45,7 +45,7 @@ void pcap_set_ts_bits(struct pcap_chip *, u32); | |||
45 | #define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff | 45 | #define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff |
46 | #define PCAP_MASK_ALL_INTERRUPT 0x01ffffff | 46 | #define PCAP_MASK_ALL_INTERRUPT 0x01ffffff |
47 | 47 | ||
48 | /* registers acessible by both pcap ports */ | 48 | /* registers accessible by both pcap ports */ |
49 | #define PCAP_REG_ISR 0x0 /* Interrupt Status */ | 49 | #define PCAP_REG_ISR 0x0 /* Interrupt Status */ |
50 | #define PCAP_REG_MSR 0x1 /* Interrupt Mask */ | 50 | #define PCAP_REG_MSR 0x1 /* Interrupt Mask */ |
51 | #define PCAP_REG_PSTAT 0x2 /* Processor Status */ | 51 | #define PCAP_REG_PSTAT 0x2 /* Processor Status */ |
@@ -67,7 +67,7 @@ void pcap_set_ts_bits(struct pcap_chip *, u32); | |||
67 | #define PCAP_REG_VENDOR_TEST1 0x1e | 67 | #define PCAP_REG_VENDOR_TEST1 0x1e |
68 | #define PCAP_REG_VENDOR_TEST2 0x1f | 68 | #define PCAP_REG_VENDOR_TEST2 0x1f |
69 | 69 | ||
70 | /* registers acessible by pcap port 1 only (a1200, e2 & e6) */ | 70 | /* registers accessible by pcap port 1 only (a1200, e2 & e6) */ |
71 | #define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */ | 71 | #define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */ |
72 | #define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */ | 72 | #define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */ |
73 | #define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */ | 73 | #define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */ |