mfd: Support AB9540 ab8500 variant

The AB9540 variant of the AB8500 is basically close enough
to use the same driver. This adds the new registers and
deviations for this new chip variant.

Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@stericsson.com>
Signed-off-by: Alex Macro <alex.macro@stericsson.com>
Signed-off-by: Michel Jaouen <michel.jaouen@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

3 files changed, 91 insertions, 2 deletions

diff --git a/include/linux/mfd/abx500/ab8500-gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h
index 488a8c920a29..2387c207ea86 100644
--- a/include/linux/mfd/abx500/ab8500-gpio.h
+++ b/include/linux/mfd/abx500/ab8500-gpio.h
@@ -10,12 +10,14 @@
 
 /*
  * Platform data to register a block: only the initial gpio/irq number.
+ * Array sizes are large enough to contain all AB8500 and AB9540 GPIO
+ * registers.
  */
 
 struct ab8500_gpio_platform_data {
         int gpio_base;
         u32 irq_base;
-        u8  config_reg[7];
+        u8  config_reg[8];
 };
 
 #endif /* _AB8500_GPIO_H */
diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h
index 10da0291f8f8..10eb50973c39 100644
--- a/include/linux/mfd/abx500/ab8500-sysctrl.h
+++ b/include/linux/mfd/abx500/ab8500-sysctrl.h
@@ -71,6 +71,13 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
 #define AB8500_SWATCTRL                 0x230
 #define AB8500_HIQCLKCTRL               0x232
 #define AB8500_VSIMSYSCLKCTRL           0x233
+#define AB9540_SYSCLK12BUFCTRL          0x234
+#define AB9540_SYSCLK12CONFCTRL         0x235
+#define AB9540_SYSCLK12BUFCTRL2         0x236
+#define AB9540_SYSCLK12BUF1VALID        0x237
+#define AB9540_SYSCLK12BUF2VALID        0x238
+#define AB9540_SYSCLK12BUF3VALID        0x239
+#define AB9540_SYSCLK12BUF4VALID        0x23A
 
 /* Bits */
 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
@@ -251,4 +258,40 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
 #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
 
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7)
+#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0
+
+#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
+#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
+#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
+#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
+#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
+#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
+#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
+
+#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0)
+#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1)
+#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2)
+#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3)
+
+#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF
+#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0
+
+#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF
+#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0
+
+#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF
+#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0
+
+#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
+#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
+
 #endif /* __AB8500_SYSCTRL_H */
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index 55eabe8b6ce6..4b2df29fb858 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -57,8 +57,11 @@ enum ab8500_version {
 
 /*
  * Interrupts
+ * Values used to index into array ab8500_irq_regoffset[] defined in
+ * drivers/mdf/ab8500-core.c
  */
-
+/* Definitions for AB8500 and AB9540 */
+/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
 #define AB8500_INT_MAIN_EXT_CH_NOT_OK   0
 #define AB8500_INT_UN_PLUG_TV_DET       1
 #define AB8500_INT_PLUG_TV_DET          2
@@ -67,6 +70,7 @@ enum ab8500_version {
 #define AB8500_INT_PON_KEY2DB_R         5
 #define AB8500_INT_PON_KEY1DB_F         6
 #define AB8500_INT_PON_KEY1DB_R         7
+/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
 #define AB8500_INT_BATT_OVV             8
 #define AB8500_INT_MAIN_CH_UNPLUG_DET   10
 #define AB8500_INT_MAIN_CH_PLUG_DET     11
@@ -74,6 +78,7 @@ enum ab8500_version {
 #define AB8500_INT_USB_ID_DET_R         13
 #define AB8500_INT_VBUS_DET_F           14
 #define AB8500_INT_VBUS_DET_R           15
+/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
 #define AB8500_INT_VBUS_CH_DROP_END     16
 #define AB8500_INT_RTC_60S              17
 #define AB8500_INT_RTC_ALARM            18
@@ -81,6 +86,7 @@ enum ab8500_version {
 #define AB8500_INT_CH_WD_EXP            21
 #define AB8500_INT_VBUS_OVV             22
 #define AB8500_INT_MAIN_CH_DROP_END     23
+/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
 #define AB8500_INT_CCN_CONV_ACC         24
 #define AB8500_INT_INT_AUD              25
 #define AB8500_INT_CCEOC                26
@@ -89,6 +95,7 @@ enum ab8500_version {
 #define AB8500_INT_LOW_BAT_R            29
 #define AB8500_INT_BUP_CHG_NOT_OK       30
 #define AB8500_INT_BUP_CHG_OK           31
+/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
 #define AB8500_INT_GP_HW_ADC_CONV_END   32
 #define AB8500_INT_ACC_DETECT_1DB_F     33
 #define AB8500_INT_ACC_DETECT_1DB_R     34
@@ -97,6 +104,7 @@ enum ab8500_version {
 #define AB8500_INT_ACC_DETECT_21DB_F    37
 #define AB8500_INT_ACC_DETECT_21DB_R    38
 #define AB8500_INT_GP_SW_ADC_CONV_END   39
+/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
 #define AB8500_INT_GPIO6R               40
 #define AB8500_INT_GPIO7R               41
 #define AB8500_INT_GPIO8R               42
@@ -105,6 +113,7 @@ enum ab8500_version {
 #define AB8500_INT_GPIO11R              45
 #define AB8500_INT_GPIO12R              46
 #define AB8500_INT_GPIO13R              47
+/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
 #define AB8500_INT_GPIO24R              48
 #define AB8500_INT_GPIO25R              49
 #define AB8500_INT_GPIO36R              50
@@ -113,6 +122,7 @@ enum ab8500_version {
 #define AB8500_INT_GPIO39R              53
 #define AB8500_INT_GPIO40R              54
 #define AB8500_INT_GPIO41R              55
+/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
 #define AB8500_INT_GPIO6F               56
 #define AB8500_INT_GPIO7F               57
 #define AB8500_INT_GPIO8F               58
@@ -121,6 +131,7 @@ enum ab8500_version {
 #define AB8500_INT_GPIO11F              61
 #define AB8500_INT_GPIO12F              62
 #define AB8500_INT_GPIO13F              63
+/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
 #define AB8500_INT_GPIO24F              64
 #define AB8500_INT_GPIO25F              65
 #define AB8500_INT_GPIO36F              66
@@ -129,6 +140,7 @@ enum ab8500_version {
 #define AB8500_INT_GPIO39F              69
 #define AB8500_INT_GPIO40F              70
 #define AB8500_INT_GPIO41F              71
+/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
 #define AB8500_INT_ADP_SOURCE_ERROR     72
 #define AB8500_INT_ADP_SINK_ERROR       73
 #define AB8500_INT_ADP_PROBE_PLUG       74
@@ -136,30 +148,62 @@ enum ab8500_version {
 #define AB8500_INT_ADP_SENSE_OFF        76
 #define AB8500_INT_USB_PHY_POWER_ERR    78
 #define AB8500_INT_USB_LINK_STATUS      79
+/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
 #define AB8500_INT_BTEMP_LOW            80
 #define AB8500_INT_BTEMP_LOW_MEDIUM     81
 #define AB8500_INT_BTEMP_MEDIUM_HIGH    82
 #define AB8500_INT_BTEMP_HIGH           83
+/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
 #define AB8500_INT_USB_CHARGER_NOT_OK   89
 #define AB8500_INT_ID_WAKEUP_R          90
 #define AB8500_INT_ID_DET_R1R           92
 #define AB8500_INT_ID_DET_R2R           93
 #define AB8500_INT_ID_DET_R3R           94
 #define AB8500_INT_ID_DET_R4R           95
+/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
 #define AB8500_INT_ID_WAKEUP_F          96
 #define AB8500_INT_ID_DET_R1F           98
 #define AB8500_INT_ID_DET_R2F           99
 #define AB8500_INT_ID_DET_R3F           100
 #define AB8500_INT_ID_DET_R4F           101
 #define AB8500_INT_USB_CHG_DET_DONE     102
+/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
 #define AB8500_INT_USB_CH_TH_PROT_F     104
 #define AB8500_INT_USB_CH_TH_PROT_R    105
 #define AB8500_INT_MAIN_CH_TH_PROT_F   106
 #define AB8500_INT_MAIN_CH_TH_PROT_R    107
 #define AB8500_INT_USB_CHARGER_NOT_OKF  111
 
+/* Definitions for AB9540 */
+/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
+#define AB9540_INT_GPIO50R              113
+#define AB9540_INT_GPIO51R              114
+#define AB9540_INT_GPIO52R              115
+#define AB9540_INT_GPIO53R              116
+#define AB9540_INT_GPIO54R              117
+#define AB9540_INT_IEXT_CH_RF_BFN_R     118
+#define AB9540_INT_IEXT_CH_RF_BFN_F     119
+/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
+#define AB9540_INT_GPIO50F              121
+#define AB9540_INT_GPIO51F              122
+#define AB9540_INT_GPIO52F              123
+#define AB9540_INT_GPIO53F              124
+#define AB9540_INT_GPIO54F              125
+
+/*
+ * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
+ * entire platform. This is a "compile time" constant so this must be set to
+ * the largest possible value that may be encountered with different AB SOCs.
+ * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
+ * which is larger.
+ */
 #define AB8500_NR_IRQS                  112
+#define AB9540_NR_IRQS                  128
+/* This is set to the roof of any AB8500 chip variant IRQ counts */
+#define AB8500_MAX_NR_IRQS              AB9540_NR_IRQS
+
 #define AB8500_NUM_IRQ_REGS             14
+#define AB9540_NUM_IRQ_REGS             17
 
 /**
  * struct ab8500 - ab8500 internal structure