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authorAnton Vorontsov <anton.vorontsov@linaro.org>2012-12-12 01:15:57 -0500
committerAnton Vorontsov <anton.vorontsov@linaro.org>2012-12-12 01:15:57 -0500
commit76d8a23b127020472207b281427d3e9f4f1227e4 (patch)
treee14d7063d96d850fb259115d6fb08cbeb98ccf88 /include/linux/mfd
parenteba3b670a9166a91be5a11fe33290dca6b9457a2 (diff)
parent1ebaf4f4e6912199f8a4e30ba3ab55da2b71bcdf (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux
The merge is merely to fix conflicts before sending a pull request. Conflicts: drivers/power/ab8500_btemp.c drivers/power/ab8500_charger.c drivers/power/ab8500_fg.c drivers/power/abx500_chargalg.c drivers/power/max8925_power.c Signed-off-by: Anton Vorontsov <anton.vorontsov@linaro.org>
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/88pm80x.h2
-rw-r--r--include/linux/mfd/abx500/ab8500.h4
-rw-r--r--include/linux/mfd/db8500-prcmu.h4
-rw-r--r--include/linux/mfd/dbx500-prcmu.h10
-rw-r--r--include/linux/mfd/pm8xxx/irq.h8
-rw-r--r--include/linux/mfd/rtsx_common.h48
-rw-r--r--include/linux/mfd/rtsx_pci.h794
7 files changed, 861 insertions, 9 deletions
diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h
index a0ca0dca1244..478672ed0c3d 100644
--- a/include/linux/mfd/88pm80x.h
+++ b/include/linux/mfd/88pm80x.h
@@ -364,6 +364,6 @@ static inline int pm80x_dev_resume(struct device *dev)
364#endif 364#endif
365 365
366extern int pm80x_init(struct i2c_client *client, 366extern int pm80x_init(struct i2c_client *client,
367 const struct i2c_device_id *id) __devinit; 367 const struct i2c_device_id *id);
368extern int pm80x_deinit(struct i2c_client *client); 368extern int pm80x_deinit(struct i2c_client *client);
369#endif /* __LINUX_MFD_88PM80X_H */ 369#endif /* __LINUX_MFD_88PM80X_H */
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index 1491044efa10..1cb5698b4d76 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -291,9 +291,9 @@ struct ab8500_platform_data {
291 struct ab8500_codec_platform_data *codec; 291 struct ab8500_codec_platform_data *codec;
292}; 292};
293 293
294extern int __devinit ab8500_init(struct ab8500 *ab8500, 294extern int ab8500_init(struct ab8500 *ab8500,
295 enum ab8500_version version); 295 enum ab8500_version version);
296extern int __devexit ab8500_exit(struct ab8500 *ab8500); 296extern int ab8500_exit(struct ab8500 *ab8500);
297 297
298extern int ab8500_suspend(struct ab8500 *ab8500); 298extern int ab8500_suspend(struct ab8500 *ab8500);
299 299
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index b82f6ee66a0b..6ee4247df11e 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -515,7 +515,6 @@ enum romcode_read prcmu_get_rc_p2a(void);
515enum ap_pwrst prcmu_get_xp70_current_state(void); 515enum ap_pwrst prcmu_get_xp70_current_state(void);
516bool prcmu_has_arm_maxopp(void); 516bool prcmu_has_arm_maxopp(void);
517struct prcmu_fw_version *prcmu_get_fw_version(void); 517struct prcmu_fw_version *prcmu_get_fw_version(void);
518int prcmu_request_ape_opp_100_voltage(bool enable);
519int prcmu_release_usb_wakeup_state(void); 518int prcmu_release_usb_wakeup_state(void);
520void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 519void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
521 struct prcmu_auto_pm_config *idle); 520 struct prcmu_auto_pm_config *idle);
@@ -564,6 +563,7 @@ int db8500_prcmu_set_arm_opp(u8 opp);
564int db8500_prcmu_get_arm_opp(void); 563int db8500_prcmu_get_arm_opp(void);
565int db8500_prcmu_set_ape_opp(u8 opp); 564int db8500_prcmu_set_ape_opp(u8 opp);
566int db8500_prcmu_get_ape_opp(void); 565int db8500_prcmu_get_ape_opp(void);
566int db8500_prcmu_request_ape_opp_100_voltage(bool enable);
567int db8500_prcmu_set_ddr_opp(u8 opp); 567int db8500_prcmu_set_ddr_opp(u8 opp);
568int db8500_prcmu_get_ddr_opp(void); 568int db8500_prcmu_get_ddr_opp(void);
569 569
@@ -610,7 +610,7 @@ static inline int db8500_prcmu_get_ape_opp(void)
610 return APE_100_OPP; 610 return APE_100_OPP;
611} 611}
612 612
613static inline int prcmu_request_ape_opp_100_voltage(bool enable) 613static inline int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
614{ 614{
615 return 0; 615 return 0;
616} 616}
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index c410d99bd667..c202d6c4d879 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -336,6 +336,11 @@ static inline int prcmu_get_ape_opp(void)
336 return db8500_prcmu_get_ape_opp(); 336 return db8500_prcmu_get_ape_opp();
337} 337}
338 338
339static inline int prcmu_request_ape_opp_100_voltage(bool enable)
340{
341 return db8500_prcmu_request_ape_opp_100_voltage(enable);
342}
343
339static inline void prcmu_system_reset(u16 reset_code) 344static inline void prcmu_system_reset(u16 reset_code)
340{ 345{
341 return db8500_prcmu_system_reset(reset_code); 346 return db8500_prcmu_system_reset(reset_code);
@@ -507,6 +512,11 @@ static inline int prcmu_get_ape_opp(void)
507 return APE_100_OPP; 512 return APE_100_OPP;
508} 513}
509 514
515static inline int prcmu_request_ape_opp_100_voltage(bool enable)
516{
517 return 0;
518}
519
510static inline int prcmu_set_arm_opp(u8 opp) 520static inline int prcmu_set_arm_opp(u8 opp)
511{ 521{
512 return 0; 522 return 0;
diff --git a/include/linux/mfd/pm8xxx/irq.h b/include/linux/mfd/pm8xxx/irq.h
index 4b21769f4483..f83d6b43ecbb 100644
--- a/include/linux/mfd/pm8xxx/irq.h
+++ b/include/linux/mfd/pm8xxx/irq.h
@@ -37,21 +37,21 @@ struct pm_irq_chip;
37 37
38#ifdef CONFIG_MFD_PM8XXX_IRQ 38#ifdef CONFIG_MFD_PM8XXX_IRQ
39int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq); 39int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq);
40struct pm_irq_chip * __devinit pm8xxx_irq_init(struct device *dev, 40struct pm_irq_chip *pm8xxx_irq_init(struct device *dev,
41 const struct pm8xxx_irq_platform_data *pdata); 41 const struct pm8xxx_irq_platform_data *pdata);
42int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip); 42int pm8xxx_irq_exit(struct pm_irq_chip *chip);
43#else 43#else
44static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq) 44static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
45{ 45{
46 return -ENXIO; 46 return -ENXIO;
47} 47}
48static inline struct pm_irq_chip * __devinit pm8xxx_irq_init( 48static inline struct pm_irq_chip *pm8xxx_irq_init(
49 const struct device *dev, 49 const struct device *dev,
50 const struct pm8xxx_irq_platform_data *pdata) 50 const struct pm8xxx_irq_platform_data *pdata)
51{ 51{
52 return ERR_PTR(-ENXIO); 52 return ERR_PTR(-ENXIO);
53} 53}
54static inline int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip) 54static inline int pm8xxx_irq_exit(struct pm_irq_chip *chip)
55{ 55{
56 return -ENXIO; 56 return -ENXIO;
57} 57}
diff --git a/include/linux/mfd/rtsx_common.h b/include/linux/mfd/rtsx_common.h
new file mode 100644
index 000000000000..a8d393e3066b
--- /dev/null
+++ b/include/linux/mfd/rtsx_common.h
@@ -0,0 +1,48 @@
1/* Driver for Realtek driver-based card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#ifndef __RTSX_COMMON_H
24#define __RTSX_COMMON_H
25
26#define DRV_NAME_RTSX_PCI "rtsx_pci"
27#define DRV_NAME_RTSX_PCI_SDMMC "rtsx_pci_sdmmc"
28#define DRV_NAME_RTSX_PCI_MS "rtsx_pci_ms"
29
30#define RTSX_REG_PAIR(addr, val) (((u32)(addr) << 16) | (u8)(val))
31
32#define RTSX_SSC_DEPTH_4M 0x01
33#define RTSX_SSC_DEPTH_2M 0x02
34#define RTSX_SSC_DEPTH_1M 0x03
35#define RTSX_SSC_DEPTH_500K 0x04
36#define RTSX_SSC_DEPTH_250K 0x05
37
38#define RTSX_SD_CARD 0
39#define RTSX_MS_CARD 1
40
41struct platform_device;
42
43struct rtsx_slot {
44 struct platform_device *p_dev;
45 void (*card_event)(struct platform_device *p_dev);
46};
47
48#endif
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
new file mode 100644
index 000000000000..060b721fcbfb
--- /dev/null
+++ b/include/linux/mfd/rtsx_pci.h
@@ -0,0 +1,794 @@
1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#ifndef __RTSX_PCI_H
24#define __RTSX_PCI_H
25
26#include <linux/sched.h>
27#include <linux/pci.h>
28
29#include "rtsx_common.h"
30
31#define MAX_RW_REG_CNT 1024
32
33/* PCI Operation Register Address */
34#define RTSX_HCBAR 0x00
35#define RTSX_HCBCTLR 0x04
36#define RTSX_HDBAR 0x08
37#define RTSX_HDBCTLR 0x0C
38#define RTSX_HAIMR 0x10
39#define RTSX_BIPR 0x14
40#define RTSX_BIER 0x18
41
42/* Host command buffer control register */
43#define STOP_CMD (0x01 << 28)
44
45/* Host data buffer control register */
46#define SDMA_MODE 0x00
47#define ADMA_MODE (0x02 << 26)
48#define STOP_DMA (0x01 << 28)
49#define TRIG_DMA (0x01 << 31)
50
51/* Host access internal memory register */
52#define HAIMR_TRANS_START (0x01 << 31)
53#define HAIMR_READ 0x00
54#define HAIMR_WRITE (0x01 << 30)
55#define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ)
56#define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE)
57#define HAIMR_TRANS_END (HAIMR_TRANS_START)
58
59/* Bus interrupt pending register */
60#define CMD_DONE_INT (1 << 31)
61#define DATA_DONE_INT (1 << 30)
62#define TRANS_OK_INT (1 << 29)
63#define TRANS_FAIL_INT (1 << 28)
64#define XD_INT (1 << 27)
65#define MS_INT (1 << 26)
66#define SD_INT (1 << 25)
67#define GPIO0_INT (1 << 24)
68#define OC_INT (1 << 23)
69#define SD_WRITE_PROTECT (1 << 19)
70#define XD_EXIST (1 << 18)
71#define MS_EXIST (1 << 17)
72#define SD_EXIST (1 << 16)
73#define DELINK_INT GPIO0_INT
74#define MS_OC_INT (1 << 23)
75#define SD_OC_INT (1 << 22)
76
77#define CARD_INT (XD_INT | MS_INT | SD_INT)
78#define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
79#define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \
80 CARD_INT | GPIO0_INT | OC_INT)
81
82#define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
83
84/* Bus interrupt enable register */
85#define CMD_DONE_INT_EN (1 << 31)
86#define DATA_DONE_INT_EN (1 << 30)
87#define TRANS_OK_INT_EN (1 << 29)
88#define TRANS_FAIL_INT_EN (1 << 28)
89#define XD_INT_EN (1 << 27)
90#define MS_INT_EN (1 << 26)
91#define SD_INT_EN (1 << 25)
92#define GPIO0_INT_EN (1 << 24)
93#define OC_INT_EN (1 << 23)
94#define DELINK_INT_EN GPIO0_INT_EN
95#define MS_OC_INT_EN (1 << 23)
96#define SD_OC_INT_EN (1 << 22)
97
98#define READ_REG_CMD 0
99#define WRITE_REG_CMD 1
100#define CHECK_REG_CMD 2
101
102/*
103 * macros for easy use
104 */
105#define rtsx_pci_writel(pcr, reg, value) \
106 iowrite32(value, (pcr)->remap_addr + reg)
107#define rtsx_pci_readl(pcr, reg) \
108 ioread32((pcr)->remap_addr + reg)
109#define rtsx_pci_writew(pcr, reg, value) \
110 iowrite16(value, (pcr)->remap_addr + reg)
111#define rtsx_pci_readw(pcr, reg) \
112 ioread16((pcr)->remap_addr + reg)
113#define rtsx_pci_writeb(pcr, reg, value) \
114 iowrite8(value, (pcr)->remap_addr + reg)
115#define rtsx_pci_readb(pcr, reg) \
116 ioread8((pcr)->remap_addr + reg)
117
118#define rtsx_pci_read_config_byte(pcr, where, val) \
119 pci_read_config_byte((pcr)->pci, where, val)
120
121#define rtsx_pci_write_config_byte(pcr, where, val) \
122 pci_write_config_byte((pcr)->pci, where, val)
123
124#define rtsx_pci_read_config_dword(pcr, where, val) \
125 pci_read_config_dword((pcr)->pci, where, val)
126
127#define rtsx_pci_write_config_dword(pcr, where, val) \
128 pci_write_config_dword((pcr)->pci, where, val)
129
130#define STATE_TRANS_NONE 0
131#define STATE_TRANS_CMD 1
132#define STATE_TRANS_BUF 2
133#define STATE_TRANS_SG 3
134
135#define TRANS_NOT_READY 0
136#define TRANS_RESULT_OK 1
137#define TRANS_RESULT_FAIL 2
138#define TRANS_NO_DEVICE 3
139
140#define RTSX_RESV_BUF_LEN 4096
141#define HOST_CMDS_BUF_LEN 1024
142#define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
143#define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8)
144#define MAX_SG_ITEM_LEN 0x80000
145
146#define HOST_TO_DEVICE 0
147#define DEVICE_TO_HOST 1
148
149#define MAX_PHASE 31
150#define RX_TUNING_CNT 3
151
152/* SG descriptor */
153#define SG_INT 0x04
154#define SG_END 0x02
155#define SG_VALID 0x01
156
157#define SG_NO_OP 0x00
158#define SG_TRANS_DATA (0x02 << 4)
159#define SG_LINK_DESC (0x03 << 4)
160
161/* SD bank voltage */
162#define SD_IO_3V3 0
163#define SD_IO_1V8 1
164
165
166/* Card Clock Enable Register */
167#define SD_CLK_EN 0x04
168#define MS_CLK_EN 0x08
169
170/* Card Select Register */
171#define SD_MOD_SEL 2
172#define MS_MOD_SEL 3
173
174/* Card Output Enable Register */
175#define SD_OUTPUT_EN 0x04
176#define MS_OUTPUT_EN 0x08
177
178/* CARD_SHARE_MODE */
179#define CARD_SHARE_MASK 0x0F
180#define CARD_SHARE_MULTI_LUN 0x00
181#define CARD_SHARE_NORMAL 0x00
182#define CARD_SHARE_48_SD 0x04
183#define CARD_SHARE_48_MS 0x08
184/* CARD_SHARE_MODE for barossa */
185#define CARD_SHARE_BAROSSA_SD 0x01
186#define CARD_SHARE_BAROSSA_MS 0x02
187
188/* SD30_DRIVE_SEL */
189#define DRIVER_TYPE_A 0x05
190#define DRIVER_TYPE_B 0x03
191#define DRIVER_TYPE_C 0x02
192#define DRIVER_TYPE_D 0x01
193
194/* FPDCTL */
195#define SSC_POWER_DOWN 0x01
196#define SD_OC_POWER_DOWN 0x02
197#define ALL_POWER_DOWN 0x07
198#define OC_POWER_DOWN 0x06
199
200/* CLK_CTL */
201#define CHANGE_CLK 0x01
202
203/* LDO_CTL */
204#define BPP_LDO_POWB 0x03
205#define BPP_LDO_ON 0x00
206#define BPP_LDO_SUSPEND 0x02
207#define BPP_LDO_OFF 0x03
208
209/* CD_PAD_CTL */
210#define CD_DISABLE_MASK 0x07
211#define MS_CD_DISABLE 0x04
212#define SD_CD_DISABLE 0x02
213#define XD_CD_DISABLE 0x01
214#define CD_DISABLE 0x07
215#define CD_ENABLE 0x00
216#define MS_CD_EN_ONLY 0x03
217#define SD_CD_EN_ONLY 0x05
218#define XD_CD_EN_ONLY 0x06
219#define FORCE_CD_LOW_MASK 0x38
220#define FORCE_CD_XD_LOW 0x08
221#define FORCE_CD_SD_LOW 0x10
222#define FORCE_CD_MS_LOW 0x20
223#define CD_AUTO_DISABLE 0x40
224
225/* SD_STAT1 */
226#define SD_CRC7_ERR 0x80
227#define SD_CRC16_ERR 0x40
228#define SD_CRC_WRITE_ERR 0x20
229#define SD_CRC_WRITE_ERR_MASK 0x1C
230#define GET_CRC_TIME_OUT 0x02
231#define SD_TUNING_COMPARE_ERR 0x01
232
233/* SD_STAT2 */
234#define SD_RSP_80CLK_TIMEOUT 0x01
235
236/* SD_BUS_STAT */
237#define SD_CLK_TOGGLE_EN 0x80
238#define SD_CLK_FORCE_STOP 0x40
239#define SD_DAT3_STATUS 0x10
240#define SD_DAT2_STATUS 0x08
241#define SD_DAT1_STATUS 0x04
242#define SD_DAT0_STATUS 0x02
243#define SD_CMD_STATUS 0x01
244
245/* SD_PAD_CTL */
246#define SD_IO_USING_1V8 0x80
247#define SD_IO_USING_3V3 0x7F
248#define TYPE_A_DRIVING 0x00
249#define TYPE_B_DRIVING 0x01
250#define TYPE_C_DRIVING 0x02
251#define TYPE_D_DRIVING 0x03
252
253/* SD_SAMPLE_POINT_CTL */
254#define DDR_FIX_RX_DAT 0x00
255#define DDR_VAR_RX_DAT 0x80
256#define DDR_FIX_RX_DAT_EDGE 0x00
257#define DDR_FIX_RX_DAT_14_DELAY 0x40
258#define DDR_FIX_RX_CMD 0x00
259#define DDR_VAR_RX_CMD 0x20
260#define DDR_FIX_RX_CMD_POS_EDGE 0x00
261#define DDR_FIX_RX_CMD_14_DELAY 0x10
262#define SD20_RX_POS_EDGE 0x00
263#define SD20_RX_14_DELAY 0x08
264#define SD20_RX_SEL_MASK 0x08
265
266/* SD_PUSH_POINT_CTL */
267#define DDR_FIX_TX_CMD_DAT 0x00
268#define DDR_VAR_TX_CMD_DAT 0x80
269#define DDR_FIX_TX_DAT_14_TSU 0x00
270#define DDR_FIX_TX_DAT_12_TSU 0x40
271#define DDR_FIX_TX_CMD_NEG_EDGE 0x00
272#define DDR_FIX_TX_CMD_14_AHEAD 0x20
273#define SD20_TX_NEG_EDGE 0x00
274#define SD20_TX_14_AHEAD 0x10
275#define SD20_TX_SEL_MASK 0x10
276#define DDR_VAR_SDCLK_POL_SWAP 0x01
277
278/* SD_TRANSFER */
279#define SD_TRANSFER_START 0x80
280#define SD_TRANSFER_END 0x40
281#define SD_STAT_IDLE 0x20
282#define SD_TRANSFER_ERR 0x10
283/* SD Transfer Mode definition */
284#define SD_TM_NORMAL_WRITE 0x00
285#define SD_TM_AUTO_WRITE_3 0x01
286#define SD_TM_AUTO_WRITE_4 0x02
287#define SD_TM_AUTO_READ_3 0x05
288#define SD_TM_AUTO_READ_4 0x06
289#define SD_TM_CMD_RSP 0x08
290#define SD_TM_AUTO_WRITE_1 0x09
291#define SD_TM_AUTO_WRITE_2 0x0A
292#define SD_TM_NORMAL_READ 0x0C
293#define SD_TM_AUTO_READ_1 0x0D
294#define SD_TM_AUTO_READ_2 0x0E
295#define SD_TM_AUTO_TUNING 0x0F
296
297/* SD_VPTX_CTL / SD_VPRX_CTL */
298#define PHASE_CHANGE 0x80
299#define PHASE_NOT_RESET 0x40
300
301/* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */
302#define DCMPS_CHANGE 0x80
303#define DCMPS_CHANGE_DONE 0x40
304#define DCMPS_ERROR 0x20
305#define DCMPS_CURRENT_PHASE 0x1F
306
307/* SD Configure 1 Register */
308#define SD_CLK_DIVIDE_0 0x00
309#define SD_CLK_DIVIDE_256 0xC0
310#define SD_CLK_DIVIDE_128 0x80
311#define SD_BUS_WIDTH_1BIT 0x00
312#define SD_BUS_WIDTH_4BIT 0x01
313#define SD_BUS_WIDTH_8BIT 0x02
314#define SD_ASYNC_FIFO_NOT_RST 0x10
315#define SD_20_MODE 0x00
316#define SD_DDR_MODE 0x04
317#define SD_30_MODE 0x08
318
319#define SD_CLK_DIVIDE_MASK 0xC0
320
321/* SD_CMD_STATE */
322#define SD_CMD_IDLE 0x80
323
324/* SD_DATA_STATE */
325#define SD_DATA_IDLE 0x80
326
327/* DCM_DRP_CTL */
328#define DCM_RESET 0x08
329#define DCM_LOCKED 0x04
330#define DCM_208M 0x00
331#define DCM_TX 0x01
332#define DCM_RX 0x02
333
334/* DCM_DRP_TRIG */
335#define DRP_START 0x80
336#define DRP_DONE 0x40
337
338/* DCM_DRP_CFG */
339#define DRP_WRITE 0x80
340#define DRP_READ 0x00
341#define DCM_WRITE_ADDRESS_50 0x50
342#define DCM_WRITE_ADDRESS_51 0x51
343#define DCM_READ_ADDRESS_00 0x00
344#define DCM_READ_ADDRESS_51 0x51
345
346/* IRQSTAT0 */
347#define DMA_DONE_INT 0x80
348#define SUSPEND_INT 0x40
349#define LINK_RDY_INT 0x20
350#define LINK_DOWN_INT 0x10
351
352/* DMACTL */
353#define DMA_RST 0x80
354#define DMA_BUSY 0x04
355#define DMA_DIR_TO_CARD 0x00
356#define DMA_DIR_FROM_CARD 0x02
357#define DMA_EN 0x01
358#define DMA_128 (0 << 4)
359#define DMA_256 (1 << 4)
360#define DMA_512 (2 << 4)
361#define DMA_1024 (3 << 4)
362#define DMA_PACK_SIZE_MASK 0x30
363
364/* SSC_CTL1 */
365#define SSC_RSTB 0x80
366#define SSC_8X_EN 0x40
367#define SSC_FIX_FRAC 0x20
368#define SSC_SEL_1M 0x00
369#define SSC_SEL_2M 0x08
370#define SSC_SEL_4M 0x10
371#define SSC_SEL_8M 0x18
372
373/* SSC_CTL2 */
374#define SSC_DEPTH_MASK 0x07
375#define SSC_DEPTH_DISALBE 0x00
376#define SSC_DEPTH_4M 0x01
377#define SSC_DEPTH_2M 0x02
378#define SSC_DEPTH_1M 0x03
379#define SSC_DEPTH_500K 0x04
380#define SSC_DEPTH_250K 0x05
381
382/* System Clock Control Register */
383#define CLK_LOW_FREQ 0x01
384
385/* System Clock Divider Register */
386#define CLK_DIV_1 0x01
387#define CLK_DIV_2 0x02
388#define CLK_DIV_4 0x03
389#define CLK_DIV_8 0x04
390
391/* MS_CFG */
392#define SAMPLE_TIME_RISING 0x00
393#define SAMPLE_TIME_FALLING 0x80
394#define PUSH_TIME_DEFAULT 0x00
395#define PUSH_TIME_ODD 0x40
396#define NO_EXTEND_TOGGLE 0x00
397#define EXTEND_TOGGLE_CHK 0x20
398#define MS_BUS_WIDTH_1 0x00
399#define MS_BUS_WIDTH_4 0x10
400#define MS_BUS_WIDTH_8 0x18
401#define MS_2K_SECTOR_MODE 0x04
402#define MS_512_SECTOR_MODE 0x00
403#define MS_TOGGLE_TIMEOUT_EN 0x00
404#define MS_TOGGLE_TIMEOUT_DISEN 0x01
405#define MS_NO_CHECK_INT 0x02
406
407/* MS_TRANS_CFG */
408#define WAIT_INT 0x80
409#define NO_WAIT_INT 0x00
410#define NO_AUTO_READ_INT_REG 0x00
411#define AUTO_READ_INT_REG 0x40
412#define MS_CRC16_ERR 0x20
413#define MS_RDY_TIMEOUT 0x10
414#define MS_INT_CMDNK 0x08
415#define MS_INT_BREQ 0x04
416#define MS_INT_ERR 0x02
417#define MS_INT_CED 0x01
418
419/* MS_TRANSFER */
420#define MS_TRANSFER_START 0x80
421#define MS_TRANSFER_END 0x40
422#define MS_TRANSFER_ERR 0x20
423#define MS_BS_STATE 0x10
424#define MS_TM_READ_BYTES 0x00
425#define MS_TM_NORMAL_READ 0x01
426#define MS_TM_WRITE_BYTES 0x04
427#define MS_TM_NORMAL_WRITE 0x05
428#define MS_TM_AUTO_READ 0x08
429#define MS_TM_AUTO_WRITE 0x0C
430
431/* SD Configure 2 Register */
432#define SD_CALCULATE_CRC7 0x00
433#define SD_NO_CALCULATE_CRC7 0x80
434#define SD_CHECK_CRC16 0x00
435#define SD_NO_CHECK_CRC16 0x40
436#define SD_NO_CHECK_WAIT_CRC_TO 0x20
437#define SD_WAIT_BUSY_END 0x08
438#define SD_NO_WAIT_BUSY_END 0x00
439#define SD_CHECK_CRC7 0x00
440#define SD_NO_CHECK_CRC7 0x04
441#define SD_RSP_LEN_0 0x00
442#define SD_RSP_LEN_6 0x01
443#define SD_RSP_LEN_17 0x02
444/* SD/MMC Response Type Definition */
445#define SD_RSP_TYPE_R0 0x04
446#define SD_RSP_TYPE_R1 0x01
447#define SD_RSP_TYPE_R1b 0x09
448#define SD_RSP_TYPE_R2 0x02
449#define SD_RSP_TYPE_R3 0x05
450#define SD_RSP_TYPE_R4 0x05
451#define SD_RSP_TYPE_R5 0x01
452#define SD_RSP_TYPE_R6 0x01
453#define SD_RSP_TYPE_R7 0x01
454
455/* SD_CONFIURE3 */
456#define SD_RSP_80CLK_TIMEOUT_EN 0x01
457
458/* Card Transfer Reset Register */
459#define SPI_STOP 0x01
460#define XD_STOP 0x02
461#define SD_STOP 0x04
462#define MS_STOP 0x08
463#define SPI_CLR_ERR 0x10
464#define XD_CLR_ERR 0x20
465#define SD_CLR_ERR 0x40
466#define MS_CLR_ERR 0x80
467
468/* Card Data Source Register */
469#define PINGPONG_BUFFER 0x01
470#define RING_BUFFER 0x00
471
472/* Card Power Control Register */
473#define PMOS_STRG_MASK 0x10
474#define PMOS_STRG_800mA 0x10
475#define PMOS_STRG_400mA 0x00
476#define SD_POWER_OFF 0x03
477#define SD_PARTIAL_POWER_ON 0x01
478#define SD_POWER_ON 0x00
479#define SD_POWER_MASK 0x03
480#define MS_POWER_OFF 0x0C
481#define MS_PARTIAL_POWER_ON 0x04
482#define MS_POWER_ON 0x00
483#define MS_POWER_MASK 0x0C
484#define BPP_POWER_OFF 0x0F
485#define BPP_POWER_5_PERCENT_ON 0x0E
486#define BPP_POWER_10_PERCENT_ON 0x0C
487#define BPP_POWER_15_PERCENT_ON 0x08
488#define BPP_POWER_ON 0x00
489#define BPP_POWER_MASK 0x0F
490
491/* PWR_GATE_CTRL */
492#define PWR_GATE_EN 0x01
493#define LDO3318_PWR_MASK 0x06
494#define LDO_ON 0x00
495#define LDO_SUSPEND 0x04
496#define LDO_OFF 0x06
497
498/* CARD_CLK_SOURCE */
499#define CRC_FIX_CLK (0x00 << 0)
500#define CRC_VAR_CLK0 (0x01 << 0)
501#define CRC_VAR_CLK1 (0x02 << 0)
502#define SD30_FIX_CLK (0x00 << 2)
503#define SD30_VAR_CLK0 (0x01 << 2)
504#define SD30_VAR_CLK1 (0x02 << 2)
505#define SAMPLE_FIX_CLK (0x00 << 4)
506#define SAMPLE_VAR_CLK0 (0x01 << 4)
507#define SAMPLE_VAR_CLK1 (0x02 << 4)
508
509#define MS_CFG 0xFD40
510#define MS_TPC 0xFD41
511#define MS_TRANS_CFG 0xFD42
512#define MS_TRANSFER 0xFD43
513#define MS_INT_REG 0xFD44
514#define MS_BYTE_CNT 0xFD45
515#define MS_SECTOR_CNT_L 0xFD46
516#define MS_SECTOR_CNT_H 0xFD47
517#define MS_DBUS_H 0xFD48
518
519#define SD_CFG1 0xFDA0
520#define SD_CFG2 0xFDA1
521#define SD_CFG3 0xFDA2
522#define SD_STAT1 0xFDA3
523#define SD_STAT2 0xFDA4
524#define SD_BUS_STAT 0xFDA5
525#define SD_PAD_CTL 0xFDA6
526#define SD_SAMPLE_POINT_CTL 0xFDA7
527#define SD_PUSH_POINT_CTL 0xFDA8
528#define SD_CMD0 0xFDA9
529#define SD_CMD1 0xFDAA
530#define SD_CMD2 0xFDAB
531#define SD_CMD3 0xFDAC
532#define SD_CMD4 0xFDAD
533#define SD_CMD5 0xFDAE
534#define SD_BYTE_CNT_L 0xFDAF
535#define SD_BYTE_CNT_H 0xFDB0
536#define SD_BLOCK_CNT_L 0xFDB1
537#define SD_BLOCK_CNT_H 0xFDB2
538#define SD_TRANSFER 0xFDB3
539#define SD_CMD_STATE 0xFDB5
540#define SD_DATA_STATE 0xFDB6
541
542#define SRCTL 0xFC13
543
544#define DCM_DRP_CTL 0xFC23
545#define DCM_DRP_TRIG 0xFC24
546#define DCM_DRP_CFG 0xFC25
547#define DCM_DRP_WR_DATA_L 0xFC26
548#define DCM_DRP_WR_DATA_H 0xFC27
549#define DCM_DRP_RD_DATA_L 0xFC28
550#define DCM_DRP_RD_DATA_H 0xFC29
551#define SD_VPCLK0_CTL 0xFC2A
552#define SD_VPCLK1_CTL 0xFC2B
553#define SD_DCMPS0_CTL 0xFC2C
554#define SD_DCMPS1_CTL 0xFC2D
555#define SD_VPTX_CTL SD_VPCLK0_CTL
556#define SD_VPRX_CTL SD_VPCLK1_CTL
557#define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
558#define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
559#define CARD_CLK_SOURCE 0xFC2E
560
561#define CARD_PWR_CTL 0xFD50
562#define CARD_CLK_SWITCH 0xFD51
563#define CARD_SHARE_MODE 0xFD52
564#define CARD_DRIVE_SEL 0xFD53
565#define CARD_STOP 0xFD54
566#define CARD_OE 0xFD55
567#define CARD_AUTO_BLINK 0xFD56
568#define CARD_GPIO_DIR 0xFD57
569#define CARD_GPIO 0xFD58
570#define CARD_DATA_SOURCE 0xFD5B
571#define CARD_SELECT 0xFD5C
572#define SD30_DRIVE_SEL 0xFD5E
573#define CARD_CLK_EN 0xFD69
574#define SDIO_CTRL 0xFD6B
575#define CD_PAD_CTL 0xFD73
576
577#define FPDCTL 0xFC00
578#define PDINFO 0xFC01
579
580#define CLK_CTL 0xFC02
581#define CLK_DIV 0xFC03
582#define CLK_SEL 0xFC04
583
584#define SSC_DIV_N_0 0xFC0F
585#define SSC_DIV_N_1 0xFC10
586#define SSC_CTL1 0xFC11
587#define SSC_CTL2 0xFC12
588
589#define RCCTL 0xFC14
590
591#define FPGA_PULL_CTL 0xFC1D
592#define OLT_LED_CTL 0xFC1E
593#define GPIO_CTL 0xFC1F
594
595#define LDO_CTL 0xFC1E
596#define SYS_VER 0xFC32
597
598#define CARD_PULL_CTL1 0xFD60
599#define CARD_PULL_CTL2 0xFD61
600#define CARD_PULL_CTL3 0xFD62
601#define CARD_PULL_CTL4 0xFD63
602#define CARD_PULL_CTL5 0xFD64
603#define CARD_PULL_CTL6 0xFD65
604
605/* PCI Express Related Registers */
606#define IRQEN0 0xFE20
607#define IRQSTAT0 0xFE21
608#define IRQEN1 0xFE22
609#define IRQSTAT1 0xFE23
610#define TLPRIEN 0xFE24
611#define TLPRISTAT 0xFE25
612#define TLPTIEN 0xFE26
613#define TLPTISTAT 0xFE27
614#define DMATC0 0xFE28
615#define DMATC1 0xFE29
616#define DMATC2 0xFE2A
617#define DMATC3 0xFE2B
618#define DMACTL 0xFE2C
619#define BCTL 0xFE2D
620#define RBBC0 0xFE2E
621#define RBBC1 0xFE2F
622#define RBDAT 0xFE30
623#define RBCTL 0xFE34
624#define CFGADDR0 0xFE35
625#define CFGADDR1 0xFE36
626#define CFGDATA0 0xFE37
627#define CFGDATA1 0xFE38
628#define CFGDATA2 0xFE39
629#define CFGDATA3 0xFE3A
630#define CFGRWCTL 0xFE3B
631#define PHYRWCTL 0xFE3C
632#define PHYDATA0 0xFE3D
633#define PHYDATA1 0xFE3E
634#define PHYADDR 0xFE3F
635#define MSGRXDATA0 0xFE40
636#define MSGRXDATA1 0xFE41
637#define MSGRXDATA2 0xFE42
638#define MSGRXDATA3 0xFE43
639#define MSGTXDATA0 0xFE44
640#define MSGTXDATA1 0xFE45
641#define MSGTXDATA2 0xFE46
642#define MSGTXDATA3 0xFE47
643#define MSGTXCTL 0xFE48
644#define PETXCFG 0xFE49
645
646#define CDRESUMECTL 0xFE52
647#define WAKE_SEL_CTL 0xFE54
648#define PME_FORCE_CTL 0xFE56
649#define ASPM_FORCE_CTL 0xFE57
650#define PM_CLK_FORCE_CTL 0xFE58
651#define PERST_GLITCH_WIDTH 0xFE5C
652#define CHANGE_LINK_STATE 0xFE5B
653#define RESET_LOAD_REG 0xFE5E
654#define EFUSE_CONTENT 0xFE5F
655#define HOST_SLEEP_STATE 0xFE60
656#define SDIO_CFG 0xFE70
657
658#define NFTS_TX_CTRL 0xFE72
659
660#define PWR_GATE_CTRL 0xFE75
661#define PWD_SUSPEND_EN 0xFE76
662#define LDO_PWR_SEL 0xFE78
663
664#define DUMMY_REG_RESET_0 0xFE90
665
666/* Memory mapping */
667#define SRAM_BASE 0xE600
668#define RBUF_BASE 0xF400
669#define PPBUF_BASE1 0xF800
670#define PPBUF_BASE2 0xFA00
671#define IMAGE_FLAG_ADDR0 0xCE80
672#define IMAGE_FLAG_ADDR1 0xCE81
673
674#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
675
676struct rtsx_pcr;
677
678struct pcr_handle {
679 struct rtsx_pcr *pcr;
680};
681
682struct pcr_ops {
683 int (*extra_init_hw)(struct rtsx_pcr *pcr);
684 int (*optimize_phy)(struct rtsx_pcr *pcr);
685 int (*turn_on_led)(struct rtsx_pcr *pcr);
686 int (*turn_off_led)(struct rtsx_pcr *pcr);
687 int (*enable_auto_blink)(struct rtsx_pcr *pcr);
688 int (*disable_auto_blink)(struct rtsx_pcr *pcr);
689 int (*card_power_on)(struct rtsx_pcr *pcr, int card);
690 int (*card_power_off)(struct rtsx_pcr *pcr, int card);
691 unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr);
692};
693
694enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
695
696struct rtsx_pcr {
697 struct pci_dev *pci;
698 unsigned int id;
699
700 /* pci resources */
701 unsigned long addr;
702 void __iomem *remap_addr;
703 int irq;
704
705 /* host reserved buffer */
706 void *rtsx_resv_buf;
707 dma_addr_t rtsx_resv_buf_addr;
708
709 void *host_cmds_ptr;
710 dma_addr_t host_cmds_addr;
711 int ci;
712
713 void *host_sg_tbl_ptr;
714 dma_addr_t host_sg_tbl_addr;
715 int sgi;
716
717 u32 bier;
718 char trans_result;
719
720 unsigned int card_inserted;
721 unsigned int card_removed;
722
723 struct delayed_work carddet_work;
724 struct delayed_work idle_work;
725
726 spinlock_t lock;
727 struct mutex pcr_mutex;
728 struct completion *done;
729 struct completion *finish_me;
730
731 unsigned int cur_clock;
732 bool ms_pmos;
733 bool remove_pci;
734 bool msi_en;
735
736#define EXTRA_CAPS_SD_SDR50 (1 << 0)
737#define EXTRA_CAPS_SD_SDR104 (1 << 1)
738#define EXTRA_CAPS_SD_DDR50 (1 << 2)
739#define EXTRA_CAPS_MMC_HSDDR (1 << 3)
740#define EXTRA_CAPS_MMC_HS200 (1 << 4)
741#define EXTRA_CAPS_MMC_8BIT (1 << 5)
742 u32 extra_caps;
743
744#define IC_VER_A 0
745#define IC_VER_B 1
746#define IC_VER_C 2
747#define IC_VER_D 3
748 u8 ic_version;
749
750 const u32 *sd_pull_ctl_enable_tbl;
751 const u32 *sd_pull_ctl_disable_tbl;
752 const u32 *ms_pull_ctl_enable_tbl;
753 const u32 *ms_pull_ctl_disable_tbl;
754
755 const struct pcr_ops *ops;
756 enum PDEV_STAT state;
757
758 int num_slots;
759 struct rtsx_slot *slots;
760};
761
762#define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
763#define PCI_VID(pcr) ((pcr)->pci->vendor)
764#define PCI_PID(pcr) ((pcr)->pci->device)
765
766void rtsx_pci_start_run(struct rtsx_pcr *pcr);
767int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
768int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
769int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
770int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
771void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
772void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
773 u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
774void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
775int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
776int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
777 int num_sg, bool read, int timeout);
778int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
779int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
780int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
781int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
782int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
783 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
784int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
785int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
786unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
787void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
788
789static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
790{
791 return (u8 *)(pcr->host_cmds_ptr);
792}
793
794#endif
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