Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Arnd Bergmann:
 "A large number of cleanups, all over the platforms.  This is dominated
  largely by the Samsung platforms (s3c, s5p, exynos) and a few of the
  others moving code out of arch/arm into more appropriate subsystems.

  The clocksource and irqchip drivers are now abstracted to the point
  where platforms that are already cleaned up do not need to even
  specify the driver they use, it can all get configured from the device
  tree as we do for normal device drivers.  The clocksource changes
  basically touch every single platform in the process.

  We further clean up the use of platform specific header files here,
  with the goal of turning more of the platforms over to being
  "multiplatform" enabled, which implies that they cannot expose their
  headers to architecture independent code any more.

  It is expected that no functional changes are part of the cleanup.
  The overall reduction in total code lines is mostly the result of
  removing broken and obsolete code."

* tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (133 commits)
  ARM: mvebu: correct gated clock documentation
  ARM: kirkwood: add missing include for nsa310
  ARM: exynos: move exynos4210-combiner to drivers/irqchip
  mfd: db8500-prcmu: update resource passing
  drivers/db8500-cpufreq: delete dangling include
  ARM: at91: remove NEOCORE 926 board
  sunxi: Cleanup the reset code and add meaningful registers defines
  ARM: S3C24XX: header mach/regs-mem.h local
  ARM: S3C24XX: header mach/regs-power.h local
  ARM: S3C24XX: header mach/regs-s3c2412-mem.h local
  ARM: S3C24XX: Remove plat-s3c24xx directory in arch/arm/
  ARM: S3C24XX: transform s3c2443 subirqs into new structure
  ARM: S3C24XX: modify s3c2443 irq init to initialize all irqs
  ARM: S3C24XX: move s3c2443 irq code to irq.c
  ARM: S3C24XX: transform s3c2416 irqs into new structure
  ARM: S3C24XX: modify s3c2416 irq init to initialize all irqs
  ARM: S3C24XX: move s3c2416 irq init to common irq code
  ARM: S3C24XX: Modify s3c_irq_wake to use the hwirq property
  ARM: S3C24XX: Move irq syscore-ops to irq-pm
  clocksource: always define CLOCKSOURCE_OF_DECLARE
  ...

2 files changed, 46 insertions, 101 deletions

diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index 6ee4247df11e..77a46ae2fc17 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -16,12 +16,6 @@
 /*
  * Registers
  */
-#define DB8500_PRCM_GPIOCR 0x138
-#define DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0     BIT(0)
-#define DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD      BIT(9)
-#define DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1     BIT(11)
-#define DB8500_PRCM_GPIOCR_SPI2_SELECT          BIT(23)
-
 #define DB8500_PRCM_LINE_VALUE 0x170
 #define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0      BIT(3)
 
@@ -493,20 +487,6 @@ struct prcmu_auto_pm_config {
         u8 sva_policy;
 };
 
-#define PRCMU_FW_PROJECT_U8500          2
-#define PRCMU_FW_PROJECT_U9500          4
-#define PRCMU_FW_PROJECT_U8500_C2       7
-#define PRCMU_FW_PROJECT_U9500_C2       11
-#define PRCMU_FW_PROJECT_U8520          13
-#define PRCMU_FW_PROJECT_U8420          14
-
-struct prcmu_fw_version {
-        u8 project;
-        u8 api_version;
-        u8 func_version;
-        u8 errata;
-};
-
 #ifdef CONFIG_MFD_DB8500_PRCMU
 
 void db8500_prcmu_early_init(void);
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index c202d6c4d879..f8bac7cfc25f 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -12,6 +12,10 @@
 #include <linux/notifier.h>
 #include <linux/err.h>
 
+/* Offset for the firmware version within the TCPM */
+#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
+#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
+
 /* PRCMU Wakeup defines */
 enum prcmu_wakeup_index {
         PRCMU_WAKEUP_INDEX_RTC,
@@ -214,12 +218,52 @@ enum ddr_pwrst {
         DDR_PWR_STATE_OFFHIGHLAT    = 0x03
 };
 
+#define DB8500_PRCMU_LEGACY_OFFSET              0xDD4
+
+struct prcmu_pdata
+{
+        bool enable_set_ddr_opp;
+        bool enable_ape_opp_100_voltage;
+        struct ab8500_platform_data *ab_platdata;
+        u32 version_offset;
+        u32 legacy_offset;
+        u32 adt_offset;
+};
+
+#define PRCMU_FW_PROJECT_U8500          2
+#define PRCMU_FW_PROJECT_U8400          3
+#define PRCMU_FW_PROJECT_U9500          4 /* Customer specific */
+#define PRCMU_FW_PROJECT_U8500_MBB      5
+#define PRCMU_FW_PROJECT_U8500_C1       6
+#define PRCMU_FW_PROJECT_U8500_C2       7
+#define PRCMU_FW_PROJECT_U8500_C3       8
+#define PRCMU_FW_PROJECT_U8500_C4       9
+#define PRCMU_FW_PROJECT_U9500_MBL      10
+#define PRCMU_FW_PROJECT_U8500_MBL      11 /* Customer specific */
+#define PRCMU_FW_PROJECT_U8500_MBL2     12 /* Customer specific */
+#define PRCMU_FW_PROJECT_U8520          13
+#define PRCMU_FW_PROJECT_U8420          14
+#define PRCMU_FW_PROJECT_A9420          20
+/* [32..63] 9540 and derivatives */
+#define PRCMU_FW_PROJECT_U9540          32
+/* [64..95] 8540 and derivatives */
+#define PRCMU_FW_PROJECT_L8540          64
+/* [96..126] 8580 and derivatives */
+#define PRCMU_FW_PROJECT_L8580          96
+
+#define PRCMU_FW_PROJECT_NAME_LEN       20
+struct prcmu_fw_version {
+        u32 project; /* Notice, project shifted with 8 on ux540 */
+        u8 api_version;
+        u8 func_version;
+        u8 errata;
+        char project_name[PRCMU_FW_PROJECT_NAME_LEN];
+};
+
 #include <linux/mfd/db8500-prcmu.h>
 
 #if defined(CONFIG_UX500_SOC_DB8500)
 
-#include <mach/id.h>
-
 static inline void __init prcmu_early_init(void)
 {
         return db8500_prcmu_early_init();
@@ -626,85 +670,6 @@ static inline void prcmu_clear(unsigned int reg, u32 bits)
         prcmu_write_masked(reg, bits, 0);
 }
 
-#if defined(CONFIG_UX500_SOC_DB8500)
-
-/**
- * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
- */
-static inline void prcmu_enable_spi2(void)
-{
-        if (cpu_is_u8500())
-                prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
-}
-
-/**
- * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
- */
-static inline void prcmu_disable_spi2(void)
-{
-        if (cpu_is_u8500())
-                prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
-}
-
-/**
- * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
- * and UARTMOD on OtherAlternateC3.
- */
-static inline void prcmu_enable_stm_mod_uart(void)
-{
-        if (cpu_is_u8500()) {
-                prcmu_set(DB8500_PRCM_GPIOCR,
-                        (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
-                         DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
-        }
-}
-
-/**
- * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
- * and UARTMOD on OtherAlternateC3.
- */
-static inline void prcmu_disable_stm_mod_uart(void)
-{
-        if (cpu_is_u8500()) {
-                prcmu_clear(DB8500_PRCM_GPIOCR,
-                        (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
-                         DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
-        }
-}
-
-/**
- * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
- */
-static inline void prcmu_enable_stm_ape(void)
-{
-        if (cpu_is_u8500()) {
-                prcmu_set(DB8500_PRCM_GPIOCR,
-                        DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
-        }
-}
-
-/**
- * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
- */
-static inline void prcmu_disable_stm_ape(void)
-{
-        if (cpu_is_u8500()) {
-                prcmu_clear(DB8500_PRCM_GPIOCR,
-                        DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
-        }
-}
-
-#else
-
-static inline void prcmu_enable_spi2(void) {}
-static inline void prcmu_disable_spi2(void) {}
-static inline void prcmu_enable_stm_mod_uart(void) {}
-static inline void prcmu_disable_stm_mod_uart(void) {}
-static inline void prcmu_enable_stm_ape(void) {}
-static inline void prcmu_disable_stm_ape(void) {}
-
-#endif
-
 /* PRCMU QoS APE OPP class */
 #define PRCMU_QOS_APE_OPP 1
 #define PRCMU_QOS_DDR_OPP 2