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authorMark Brown <broonie@opensource.wolfsonmicro.com>2011-08-08 01:56:19 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-08-08 01:56:19 -0400
commit18d4ed4342c14ebeebe60d267b171053efcdfa87 (patch)
treef315e77f66cbb70869e2f80cde5c18380a80901e /include/linux/mfd
parent722d0daf2b607a32dad1357bf797e3803484af0a (diff)
parent22de4534ae12d61257fc0e53d2571686b03305bc (diff)
Merge branch 'for-3.1' into for-3.2
Conflict due to the fix for the register map failure - taken the for-3.1 version. Conflicts: sound/soc/codecs/sgtl5000.c
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/aat2870.h181
-rw-r--r--include/linux/mfd/ab8500.h8
-rw-r--r--include/linux/mfd/ds1wm.h7
-rw-r--r--include/linux/mfd/max8997.h7
-rw-r--r--include/linux/mfd/max8998.h12
-rw-r--r--include/linux/mfd/pm8xxx/rtc.h25
-rw-r--r--include/linux/mfd/stmpe.h3
-rw-r--r--include/linux/mfd/tmio.h8
-rw-r--r--include/linux/mfd/tps65910.h3
-rw-r--r--include/linux/mfd/tps65912.h327
-rw-r--r--include/linux/mfd/twl4030-audio.h (renamed from include/linux/mfd/twl4030-codec.h)16
-rw-r--r--include/linux/mfd/twl6040.h228
-rw-r--r--include/linux/mfd/wm831x/core.h119
-rw-r--r--include/linux/mfd/wm831x/pdata.h3
14 files changed, 928 insertions, 19 deletions
diff --git a/include/linux/mfd/aat2870.h b/include/linux/mfd/aat2870.h
new file mode 100644
index 000000000000..f7316c29bdec
--- /dev/null
+++ b/include/linux/mfd/aat2870.h
@@ -0,0 +1,181 @@
1/*
2 * linux/include/linux/mfd/aat2870.h
3 *
4 * Copyright (c) 2011, NVIDIA Corporation.
5 * Author: Jin Park <jinyoungp@nvidia.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 */
21
22#ifndef __LINUX_MFD_AAT2870_H
23#define __LINUX_MFD_AAT2870_H
24
25#include <linux/debugfs.h>
26#include <linux/i2c.h>
27
28/* Register offsets */
29#define AAT2870_BL_CH_EN 0x00
30#define AAT2870_BLM 0x01
31#define AAT2870_BLS 0x02
32#define AAT2870_BL1 0x03
33#define AAT2870_BL2 0x04
34#define AAT2870_BL3 0x05
35#define AAT2870_BL4 0x06
36#define AAT2870_BL5 0x07
37#define AAT2870_BL6 0x08
38#define AAT2870_BL7 0x09
39#define AAT2870_BL8 0x0A
40#define AAT2870_FLR 0x0B
41#define AAT2870_FM 0x0C
42#define AAT2870_FS 0x0D
43#define AAT2870_ALS_CFG0 0x0E
44#define AAT2870_ALS_CFG1 0x0F
45#define AAT2870_ALS_CFG2 0x10
46#define AAT2870_AMB 0x11
47#define AAT2870_ALS0 0x12
48#define AAT2870_ALS1 0x13
49#define AAT2870_ALS2 0x14
50#define AAT2870_ALS3 0x15
51#define AAT2870_ALS4 0x16
52#define AAT2870_ALS5 0x17
53#define AAT2870_ALS6 0x18
54#define AAT2870_ALS7 0x19
55#define AAT2870_ALS8 0x1A
56#define AAT2870_ALS9 0x1B
57#define AAT2870_ALSA 0x1C
58#define AAT2870_ALSB 0x1D
59#define AAT2870_ALSC 0x1E
60#define AAT2870_ALSD 0x1F
61#define AAT2870_ALSE 0x20
62#define AAT2870_ALSF 0x21
63#define AAT2870_SUB_SET 0x22
64#define AAT2870_SUB_CTRL 0x23
65#define AAT2870_LDO_AB 0x24
66#define AAT2870_LDO_CD 0x25
67#define AAT2870_LDO_EN 0x26
68#define AAT2870_REG_NUM 0x27
69
70/* Device IDs */
71enum aat2870_id {
72 AAT2870_ID_BL,
73 AAT2870_ID_LDOA,
74 AAT2870_ID_LDOB,
75 AAT2870_ID_LDOC,
76 AAT2870_ID_LDOD
77};
78
79/* Backlight channels */
80#define AAT2870_BL_CH1 0x01
81#define AAT2870_BL_CH2 0x02
82#define AAT2870_BL_CH3 0x04
83#define AAT2870_BL_CH4 0x08
84#define AAT2870_BL_CH5 0x10
85#define AAT2870_BL_CH6 0x20
86#define AAT2870_BL_CH7 0x40
87#define AAT2870_BL_CH8 0x80
88#define AAT2870_BL_CH_ALL 0xFF
89
90/* Backlight current magnitude (mA) */
91enum aat2870_current {
92 AAT2870_CURRENT_0_45 = 1,
93 AAT2870_CURRENT_0_90,
94 AAT2870_CURRENT_1_80,
95 AAT2870_CURRENT_2_70,
96 AAT2870_CURRENT_3_60,
97 AAT2870_CURRENT_4_50,
98 AAT2870_CURRENT_5_40,
99 AAT2870_CURRENT_6_30,
100 AAT2870_CURRENT_7_20,
101 AAT2870_CURRENT_8_10,
102 AAT2870_CURRENT_9_00,
103 AAT2870_CURRENT_9_90,
104 AAT2870_CURRENT_10_8,
105 AAT2870_CURRENT_11_7,
106 AAT2870_CURRENT_12_6,
107 AAT2870_CURRENT_13_5,
108 AAT2870_CURRENT_14_4,
109 AAT2870_CURRENT_15_3,
110 AAT2870_CURRENT_16_2,
111 AAT2870_CURRENT_17_1,
112 AAT2870_CURRENT_18_0,
113 AAT2870_CURRENT_18_9,
114 AAT2870_CURRENT_19_8,
115 AAT2870_CURRENT_20_7,
116 AAT2870_CURRENT_21_6,
117 AAT2870_CURRENT_22_5,
118 AAT2870_CURRENT_23_4,
119 AAT2870_CURRENT_24_3,
120 AAT2870_CURRENT_25_2,
121 AAT2870_CURRENT_26_1,
122 AAT2870_CURRENT_27_0,
123 AAT2870_CURRENT_27_9
124};
125
126struct aat2870_register {
127 bool readable;
128 bool writeable;
129 u8 value;
130};
131
132struct aat2870_data {
133 struct device *dev;
134 struct i2c_client *client;
135
136 struct mutex io_lock;
137 struct aat2870_register *reg_cache; /* register cache */
138 int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
139 bool is_enable;
140
141 /* init and uninit for platform specified */
142 int (*init)(struct aat2870_data *aat2870);
143 void (*uninit)(struct aat2870_data *aat2870);
144
145 /* i2c io funcntions */
146 int (*read)(struct aat2870_data *aat2870, u8 addr, u8 *val);
147 int (*write)(struct aat2870_data *aat2870, u8 addr, u8 val);
148 int (*update)(struct aat2870_data *aat2870, u8 addr, u8 mask, u8 val);
149
150 /* for debugfs */
151 struct dentry *dentry_root;
152 struct dentry *dentry_reg;
153};
154
155struct aat2870_subdev_info {
156 int id;
157 const char *name;
158 void *platform_data;
159};
160
161struct aat2870_platform_data {
162 int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
163
164 struct aat2870_subdev_info *subdevs;
165 int num_subdevs;
166
167 /* init and uninit for platform specified */
168 int (*init)(struct aat2870_data *aat2870);
169 void (*uninit)(struct aat2870_data *aat2870);
170};
171
172struct aat2870_bl_platform_data {
173 /* backlight channels, default is AAT2870_BL_CH_ALL */
174 int channels;
175 /* backlight current magnitude, default is AAT2870_CURRENT_27_9 */
176 int max_current;
177 /* maximum brightness, default is 255 */
178 int max_brightness;
179};
180
181#endif /* __LINUX_MFD_AAT2870_H */
diff --git a/include/linux/mfd/ab8500.h b/include/linux/mfd/ab8500.h
index b31843075198..838c6b487cc5 100644
--- a/include/linux/mfd/ab8500.h
+++ b/include/linux/mfd/ab8500.h
@@ -28,6 +28,7 @@
28#define AB8500_INTERRUPT 0xE 28#define AB8500_INTERRUPT 0xE
29#define AB8500_RTC 0xF 29#define AB8500_RTC 0xF
30#define AB8500_MISC 0x10 30#define AB8500_MISC 0x10
31#define AB8500_DEVELOPMENT 0x11
31#define AB8500_DEBUG 0x12 32#define AB8500_DEBUG 0x12
32#define AB8500_PROD_TEST 0x13 33#define AB8500_PROD_TEST 0x13
33#define AB8500_OTP_EMUL 0x15 34#define AB8500_OTP_EMUL 0x15
@@ -74,13 +75,6 @@
74#define AB8500_INT_ACC_DETECT_21DB_F 37 75#define AB8500_INT_ACC_DETECT_21DB_F 37
75#define AB8500_INT_ACC_DETECT_21DB_R 38 76#define AB8500_INT_ACC_DETECT_21DB_R 38
76#define AB8500_INT_GP_SW_ADC_CONV_END 39 77#define AB8500_INT_GP_SW_ADC_CONV_END 39
77#define AB8500_INT_ACC_DETECT_1DB_F 33
78#define AB8500_INT_ACC_DETECT_1DB_R 34
79#define AB8500_INT_ACC_DETECT_22DB_F 35
80#define AB8500_INT_ACC_DETECT_22DB_R 36
81#define AB8500_INT_ACC_DETECT_21DB_F 37
82#define AB8500_INT_ACC_DETECT_21DB_R 38
83#define AB8500_INT_GP_SW_ADC_CONV_END 39
84#define AB8500_INT_GPIO6R 40 78#define AB8500_INT_GPIO6R 40
85#define AB8500_INT_GPIO7R 41 79#define AB8500_INT_GPIO7R 41
86#define AB8500_INT_GPIO8R 42 80#define AB8500_INT_GPIO8R 42
diff --git a/include/linux/mfd/ds1wm.h b/include/linux/mfd/ds1wm.h
index be469a357cbb..38a372a0e285 100644
--- a/include/linux/mfd/ds1wm.h
+++ b/include/linux/mfd/ds1wm.h
@@ -3,4 +3,11 @@
3struct ds1wm_driver_data { 3struct ds1wm_driver_data {
4 int active_high; 4 int active_high;
5 int clock_rate; 5 int clock_rate;
6 /* in milliseconds, the amount of time to */
7 /* sleep following a reset pulse. Zero */
8 /* should work if your bus devices recover*/
9 /* time respects the 1-wire spec since the*/
10 /* ds1wm implements the precise timings of*/
11 /* a reset pulse/presence detect sequence.*/
12 unsigned int reset_recover_delay;
6}; 13};
diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
index 60931d089422..0bbd13dbe336 100644
--- a/include/linux/mfd/max8997.h
+++ b/include/linux/mfd/max8997.h
@@ -107,11 +107,16 @@ struct max8997_platform_data {
107 unsigned int buck5_voltage[8]; 107 unsigned int buck5_voltage[8];
108 bool buck5_gpiodvs; 108 bool buck5_gpiodvs;
109 109
110 /* ---- Charger control ---- */
111 /* eoc stands for 'end of charge' */
112 int eoc_mA; /* 50 ~ 200mA by 10mA step */
113 /* charge Full Timeout */
114 int timeout; /* 0 (no timeout), 5, 6, 7 hours */
115
110 /* MUIC: Not implemented */ 116 /* MUIC: Not implemented */
111 /* HAPTIC: Not implemented */ 117 /* HAPTIC: Not implemented */
112 /* RTC: Not implemented */ 118 /* RTC: Not implemented */
113 /* Flash: Not implemented */ 119 /* Flash: Not implemented */
114 /* Charger control: Not implemented */
115}; 120};
116 121
117#endif /* __LINUX_MFD_MAX8998_H */ 122#endif /* __LINUX_MFD_MAX8998_H */
diff --git a/include/linux/mfd/max8998.h b/include/linux/mfd/max8998.h
index 61daa167b576..f4f0dfa4698a 100644
--- a/include/linux/mfd/max8998.h
+++ b/include/linux/mfd/max8998.h
@@ -87,6 +87,15 @@ struct max8998_regulator_data {
87 * @wakeup: Allow to wake up from suspend 87 * @wakeup: Allow to wake up from suspend
88 * @rtc_delay: LP3974 RTC chip bug that requires delay after a register 88 * @rtc_delay: LP3974 RTC chip bug that requires delay after a register
89 * write before reading it. 89 * write before reading it.
90 * @eoc: End of Charge Level in percent: 10% ~ 45% by 5% step
91 * If it equals 0, leave it unchanged.
92 * Otherwise, it is a invalid value.
93 * @restart: Restart Level in mV: 100, 150, 200, and -1 for disable.
94 * If it equals 0, leave it unchanged.
95 * Otherwise, it is a invalid value.
96 * @timeout: Full Timeout in hours: 5, 6, 7, and -1 for disable.
97 * If it equals 0, leave it unchanged.
98 * Otherwise, leave it unchanged.
90 */ 99 */
91struct max8998_platform_data { 100struct max8998_platform_data {
92 struct max8998_regulator_data *regulators; 101 struct max8998_regulator_data *regulators;
@@ -107,6 +116,9 @@ struct max8998_platform_data {
107 int buck2_default_idx; 116 int buck2_default_idx;
108 bool wakeup; 117 bool wakeup;
109 bool rtc_delay; 118 bool rtc_delay;
119 int eoc;
120 int restart;
121 int timeout;
110}; 122};
111 123
112#endif /* __LINUX_MFD_MAX8998_H */ 124#endif /* __LINUX_MFD_MAX8998_H */
diff --git a/include/linux/mfd/pm8xxx/rtc.h b/include/linux/mfd/pm8xxx/rtc.h
new file mode 100644
index 000000000000..14f1983eaecc
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/rtc.h
@@ -0,0 +1,25 @@
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __RTC_PM8XXX_H__
14#define __RTC_PM8XXX_H__
15
16#define PM8XXX_RTC_DEV_NAME "rtc-pm8xxx"
17/**
18 * struct pm8xxx_rtc_pdata - RTC driver platform data
19 * @rtc_write_enable: variable stating RTC write capability
20 */
21struct pm8xxx_rtc_platform_data {
22 bool rtc_write_enable;
23};
24
25#endif /* __RTC_PM8XXX_H__ */
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index e762c270d8d4..be1af7c42e57 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -57,6 +57,7 @@ struct stmpe_variant_info;
57 * @irq_lock: IRQ bus lock 57 * @irq_lock: IRQ bus lock
58 * @dev: device, mostly for dev_dbg() 58 * @dev: device, mostly for dev_dbg()
59 * @i2c: i2c client 59 * @i2c: i2c client
60 * @partnum: part number
60 * @variant: the detected STMPE model number 61 * @variant: the detected STMPE model number
61 * @regs: list of addresses of registers which are at different addresses on 62 * @regs: list of addresses of registers which are at different addresses on
62 * different variants. Indexed by one of STMPE_IDX_*. 63 * different variants. Indexed by one of STMPE_IDX_*.
@@ -121,6 +122,8 @@ struct stmpe_keypad_platform_data {
121 * @norequest_mask: bitmask specifying which GPIOs should _not_ be 122 * @norequest_mask: bitmask specifying which GPIOs should _not_ be
122 * requestable due to different usage (e.g. touch, keypad) 123 * requestable due to different usage (e.g. touch, keypad)
123 * STMPE_GPIO_NOREQ_* macros can be used here. 124 * STMPE_GPIO_NOREQ_* macros can be used here.
125 * @setup: board specific setup callback.
126 * @remove: board specific remove callback
124 */ 127 */
125struct stmpe_gpio_platform_data { 128struct stmpe_gpio_platform_data {
126 int gpio_base; 129 int gpio_base;
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index 5a90266c3a5a..0dc98044d8b7 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -68,6 +68,11 @@
68 * controller and report the event to the driver. 68 * controller and report the event to the driver.
69 */ 69 */
70#define TMIO_MMC_HAS_COLD_CD (1 << 3) 70#define TMIO_MMC_HAS_COLD_CD (1 << 3)
71/*
72 * Some controllers require waiting for the SD bus to become
73 * idle before writing to some registers.
74 */
75#define TMIO_MMC_HAS_IDLE_WAIT (1 << 4)
71 76
72int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); 77int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
73int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); 78int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
@@ -80,6 +85,8 @@ struct tmio_mmc_dma {
80 int alignment_shift; 85 int alignment_shift;
81}; 86};
82 87
88struct tmio_mmc_host;
89
83/* 90/*
84 * data for the MMC controller 91 * data for the MMC controller
85 */ 92 */
@@ -94,6 +101,7 @@ struct tmio_mmc_data {
94 void (*set_pwr)(struct platform_device *host, int state); 101 void (*set_pwr)(struct platform_device *host, int state);
95 void (*set_clk_div)(struct platform_device *host, int state); 102 void (*set_clk_div)(struct platform_device *host, int state);
96 int (*get_cd)(struct platform_device *host); 103 int (*get_cd)(struct platform_device *host);
104 int (*write16_hook)(struct tmio_mmc_host *host, int addr);
97}; 105};
98 106
99static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata) 107static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata)
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index 8bb85b930c07..82b4c8801a4f 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -269,7 +269,7 @@
269#define LDO1_SEL_MASK 0xFC 269#define LDO1_SEL_MASK 0xFC
270#define LDO3_SEL_MASK 0x7C 270#define LDO3_SEL_MASK 0x7C
271#define LDO_MIN_VOLT 1000 271#define LDO_MIN_VOLT 1000
272#define LDO_MAX_VOLT 3300; 272#define LDO_MAX_VOLT 3300
273 273
274 274
275/*Register VDIG1 (0x80) register.RegisterDescription */ 275/*Register VDIG1 (0x80) register.RegisterDescription */
@@ -791,6 +791,7 @@ int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
791void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); 791void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
792int tps65910_irq_init(struct tps65910 *tps65910, int irq, 792int tps65910_irq_init(struct tps65910 *tps65910, int irq,
793 struct tps65910_platform_data *pdata); 793 struct tps65910_platform_data *pdata);
794int tps65910_irq_exit(struct tps65910 *tps65910);
794 795
795static inline int tps65910_chip_id(struct tps65910 *tps65910) 796static inline int tps65910_chip_id(struct tps65910 *tps65910)
796{ 797{
diff --git a/include/linux/mfd/tps65912.h b/include/linux/mfd/tps65912.h
new file mode 100644
index 000000000000..aaceab402ec5
--- /dev/null
+++ b/include/linux/mfd/tps65912.h
@@ -0,0 +1,327 @@
1/*
2 * tps65912.h -- TI TPS6591x
3 *
4 * Copyright 2011 Texas Instruments Inc.
5 *
6 * Author: Margarita Olaya <magi@slimlogic.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __LINUX_MFD_TPS65912_H
16#define __LINUX_MFD_TPS65912_H
17
18/* TPS regulator type list */
19#define REGULATOR_LDO 0
20#define REGULATOR_DCDC 1
21
22/*
23 * List of registers for TPS65912
24 */
25
26#define TPS65912_DCDC1_CTRL 0x00
27#define TPS65912_DCDC2_CTRL 0x01
28#define TPS65912_DCDC3_CTRL 0x02
29#define TPS65912_DCDC4_CTRL 0x03
30#define TPS65912_DCDC1_OP 0x04
31#define TPS65912_DCDC1_AVS 0x05
32#define TPS65912_DCDC1_LIMIT 0x06
33#define TPS65912_DCDC2_OP 0x07
34#define TPS65912_DCDC2_AVS 0x08
35#define TPS65912_DCDC2_LIMIT 0x09
36#define TPS65912_DCDC3_OP 0x0A
37#define TPS65912_DCDC3_AVS 0x0B
38#define TPS65912_DCDC3_LIMIT 0x0C
39#define TPS65912_DCDC4_OP 0x0D
40#define TPS65912_DCDC4_AVS 0x0E
41#define TPS65912_DCDC4_LIMIT 0x0F
42#define TPS65912_LDO1_OP 0x10
43#define TPS65912_LDO1_AVS 0x11
44#define TPS65912_LDO1_LIMIT 0x12
45#define TPS65912_LDO2_OP 0x13
46#define TPS65912_LDO2_AVS 0x14
47#define TPS65912_LDO2_LIMIT 0x15
48#define TPS65912_LDO3_OP 0x16
49#define TPS65912_LDO3_AVS 0x17
50#define TPS65912_LDO3_LIMIT 0x18
51#define TPS65912_LDO4_OP 0x19
52#define TPS65912_LDO4_AVS 0x1A
53#define TPS65912_LDO4_LIMIT 0x1B
54#define TPS65912_LDO5 0x1C
55#define TPS65912_LDO6 0x1D
56#define TPS65912_LDO7 0x1E
57#define TPS65912_LDO8 0x1F
58#define TPS65912_LDO9 0x20
59#define TPS65912_LDO10 0x21
60#define TPS65912_THRM 0x22
61#define TPS65912_CLK32OUT 0x23
62#define TPS65912_DEVCTRL 0x24
63#define TPS65912_DEVCTRL2 0x25
64#define TPS65912_I2C_SPI_CFG 0x26
65#define TPS65912_KEEP_ON 0x27
66#define TPS65912_KEEP_ON2 0x28
67#define TPS65912_SET_OFF1 0x29
68#define TPS65912_SET_OFF2 0x2A
69#define TPS65912_DEF_VOLT 0x2B
70#define TPS65912_DEF_VOLT_MAPPING 0x2C
71#define TPS65912_DISCHARGE 0x2D
72#define TPS65912_DISCHARGE2 0x2E
73#define TPS65912_EN1_SET1 0x2F
74#define TPS65912_EN1_SET2 0x30
75#define TPS65912_EN2_SET1 0x31
76#define TPS65912_EN2_SET2 0x32
77#define TPS65912_EN3_SET1 0x33
78#define TPS65912_EN3_SET2 0x34
79#define TPS65912_EN4_SET1 0x35
80#define TPS65912_EN4_SET2 0x36
81#define TPS65912_PGOOD 0x37
82#define TPS65912_PGOOD2 0x38
83#define TPS65912_INT_STS 0x39
84#define TPS65912_INT_MSK 0x3A
85#define TPS65912_INT_STS2 0x3B
86#define TPS65912_INT_MSK2 0x3C
87#define TPS65912_INT_STS3 0x3D
88#define TPS65912_INT_MSK3 0x3E
89#define TPS65912_INT_STS4 0x3F
90#define TPS65912_INT_MSK4 0x40
91#define TPS65912_GPIO1 0x41
92#define TPS65912_GPIO2 0x42
93#define TPS65912_GPIO3 0x43
94#define TPS65912_GPIO4 0x44
95#define TPS65912_GPIO5 0x45
96#define TPS65912_VMON 0x46
97#define TPS65912_LEDA_CTRL1 0x47
98#define TPS65912_LEDA_CTRL2 0x48
99#define TPS65912_LEDA_CTRL3 0x49
100#define TPS65912_LEDA_CTRL4 0x4A
101#define TPS65912_LEDA_CTRL5 0x4B
102#define TPS65912_LEDA_CTRL6 0x4C
103#define TPS65912_LEDA_CTRL7 0x4D
104#define TPS65912_LEDA_CTRL8 0x4E
105#define TPS65912_LEDB_CTRL1 0x4F
106#define TPS65912_LEDB_CTRL2 0x50
107#define TPS65912_LEDB_CTRL3 0x51
108#define TPS65912_LEDB_CTRL4 0x52
109#define TPS65912_LEDB_CTRL5 0x53
110#define TPS65912_LEDB_CTRL6 0x54
111#define TPS65912_LEDB_CTRL7 0x55
112#define TPS65912_LEDB_CTRL8 0x56
113#define TPS65912_LEDC_CTRL1 0x57
114#define TPS65912_LEDC_CTRL2 0x58
115#define TPS65912_LEDC_CTRL3 0x59
116#define TPS65912_LEDC_CTRL4 0x5A
117#define TPS65912_LEDC_CTRL5 0x5B
118#define TPS65912_LEDC_CTRL6 0x5C
119#define TPS65912_LEDC_CTRL7 0x5D
120#define TPS65912_LEDC_CTRL8 0x5E
121#define TPS65912_LED_RAMP_UP_TIME 0x5F
122#define TPS65912_LED_RAMP_DOWN_TIME 0x60
123#define TPS65912_LED_SEQ_EN 0x61
124#define TPS65912_LOADSWITCH 0x62
125#define TPS65912_SPARE 0x63
126#define TPS65912_VERNUM 0x64
127#define TPS6591X_MAX_REGISTER 0x64
128
129/* IRQ Definitions */
130#define TPS65912_IRQ_PWRHOLD_F 0
131#define TPS65912_IRQ_VMON 1
132#define TPS65912_IRQ_PWRON 2
133#define TPS65912_IRQ_PWRON_LP 3
134#define TPS65912_IRQ_PWRHOLD_R 4
135#define TPS65912_IRQ_HOTDIE 5
136#define TPS65912_IRQ_GPIO1_R 6
137#define TPS65912_IRQ_GPIO1_F 7
138#define TPS65912_IRQ_GPIO2_R 8
139#define TPS65912_IRQ_GPIO2_F 9
140#define TPS65912_IRQ_GPIO3_R 10
141#define TPS65912_IRQ_GPIO3_F 11
142#define TPS65912_IRQ_GPIO4_R 12
143#define TPS65912_IRQ_GPIO4_F 13
144#define TPS65912_IRQ_GPIO5_R 14
145#define TPS65912_IRQ_GPIO5_F 15
146#define TPS65912_IRQ_PGOOD_DCDC1 16
147#define TPS65912_IRQ_PGOOD_DCDC2 17
148#define TPS65912_IRQ_PGOOD_DCDC3 18
149#define TPS65912_IRQ_PGOOD_DCDC4 19
150#define TPS65912_IRQ_PGOOD_LDO1 20
151#define TPS65912_IRQ_PGOOD_LDO2 21
152#define TPS65912_IRQ_PGOOD_LDO3 22
153#define TPS65912_IRQ_PGOOD_LDO4 23
154#define TPS65912_IRQ_PGOOD_LDO5 24
155#define TPS65912_IRQ_PGOOD_LDO6 25
156#define TPS65912_IRQ_PGOOD_LDO7 26
157#define TPS65912_IRQ_PGOOD_LD08 27
158#define TPS65912_IRQ_PGOOD_LDO9 28
159#define TPS65912_IRQ_PGOOD_LDO10 29
160
161#define TPS65912_NUM_IRQ 30
162
163/* GPIO 1 and 2 Register Definitions */
164#define GPIO_SLEEP_MASK 0x80
165#define GPIO_SLEEP_SHIFT 7
166#define GPIO_DEB_MASK 0x10
167#define GPIO_DEB_SHIFT 4
168#define GPIO_CFG_MASK 0x04
169#define GPIO_CFG_SHIFT 2
170#define GPIO_STS_MASK 0x02
171#define GPIO_STS_SHIFT 1
172#define GPIO_SET_MASK 0x01
173#define GPIO_SET_SHIFT 0
174
175/* GPIO 3 Register Definitions */
176#define GPIO3_SLEEP_MASK 0x80
177#define GPIO3_SLEEP_SHIFT 7
178#define GPIO3_SEL_MASK 0x40
179#define GPIO3_SEL_SHIFT 6
180#define GPIO3_ODEN_MASK 0x20
181#define GPIO3_ODEN_SHIFT 5
182#define GPIO3_DEB_MASK 0x10
183#define GPIO3_DEB_SHIFT 4
184#define GPIO3_PDEN_MASK 0x08
185#define GPIO3_PDEN_SHIFT 3
186#define GPIO3_CFG_MASK 0x04
187#define GPIO3_CFG_SHIFT 2
188#define GPIO3_STS_MASK 0x02
189#define GPIO3_STS_SHIFT 1
190#define GPIO3_SET_MASK 0x01
191#define GPIO3_SET_SHIFT 0
192
193/* GPIO 4 Register Definitions */
194#define GPIO4_SLEEP_MASK 0x80
195#define GPIO4_SLEEP_SHIFT 7
196#define GPIO4_SEL_MASK 0x40
197#define GPIO4_SEL_SHIFT 6
198#define GPIO4_ODEN_MASK 0x20
199#define GPIO4_ODEN_SHIFT 5
200#define GPIO4_DEB_MASK 0x10
201#define GPIO4_DEB_SHIFT 4
202#define GPIO4_PDEN_MASK 0x08
203#define GPIO4_PDEN_SHIFT 3
204#define GPIO4_CFG_MASK 0x04
205#define GPIO4_CFG_SHIFT 2
206#define GPIO4_STS_MASK 0x02
207#define GPIO4_STS_SHIFT 1
208#define GPIO4_SET_MASK 0x01
209#define GPIO4_SET_SHIFT 0
210
211/* Register THERM (0x80) register.RegisterDescription */
212#define THERM_THERM_HD_MASK 0x20
213#define THERM_THERM_HD_SHIFT 5
214#define THERM_THERM_TS_MASK 0x10
215#define THERM_THERM_TS_SHIFT 4
216#define THERM_THERM_HDSEL_MASK 0x0C
217#define THERM_THERM_HDSEL_SHIFT 2
218#define THERM_RSVD1_MASK 0x02
219#define THERM_RSVD1_SHIFT 1
220#define THERM_THERM_STATE_MASK 0x01
221#define THERM_THERM_STATE_SHIFT 0
222
223/* Register DCDCCTRL1 register.RegisterDescription */
224#define DCDCCTRL_VCON_ENABLE_MASK 0x80
225#define DCDCCTRL_VCON_ENABLE_SHIFT 7
226#define DCDCCTRL_VCON_RANGE1_MASK 0x40
227#define DCDCCTRL_VCON_RANGE1_SHIFT 6
228#define DCDCCTRL_VCON_RANGE0_MASK 0x20
229#define DCDCCTRL_VCON_RANGE0_SHIFT 5
230#define DCDCCTRL_TSTEP2_MASK 0x10
231#define DCDCCTRL_TSTEP2_SHIFT 4
232#define DCDCCTRL_TSTEP1_MASK 0x08
233#define DCDCCTRL_TSTEP1_SHIFT 3
234#define DCDCCTRL_TSTEP0_MASK 0x04
235#define DCDCCTRL_TSTEP0_SHIFT 2
236#define DCDCCTRL_DCDC1_MODE_MASK 0x02
237#define DCDCCTRL_DCDC1_MODE_SHIFT 1
238
239/* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */
240#define DCDCCTRL_TSTEP2_MASK 0x10
241#define DCDCCTRL_TSTEP2_SHIFT 4
242#define DCDCCTRL_TSTEP1_MASK 0x08
243#define DCDCCTRL_TSTEP1_SHIFT 3
244#define DCDCCTRL_TSTEP0_MASK 0x04
245#define DCDCCTRL_TSTEP0_SHIFT 2
246#define DCDCCTRL_DCDC_MODE_MASK 0x02
247#define DCDCCTRL_DCDC_MODE_SHIFT 1
248#define DCDCCTRL_RSVD0_MASK 0x01
249#define DCDCCTRL_RSVD0_SHIFT 0
250
251/* Register DCDCCTRL4 register.RegisterDescription */
252#define DCDCCTRL_RAMP_TIME_MASK 0x01
253#define DCDCCTRL_RAMP_TIME_SHIFT 0
254
255/* Register DCDCx_AVS */
256#define DCDC_AVS_ENABLE_MASK 0x80
257#define DCDC_AVS_ENABLE_SHIFT 7
258#define DCDC_AVS_ECO_MASK 0x40
259#define DCDC_AVS_ECO_SHIFT 6
260
261/* Register DCDCx_LIMIT */
262#define DCDC_LIMIT_RANGE_MASK 0xC0
263#define DCDC_LIMIT_RANGE_SHIFT 6
264#define DCDC_LIMIT_MAX_SEL_MASK 0x3F
265#define DCDC_LIMIT_MAX_SEL_SHIFT 0
266
267/**
268 * struct tps65912_board
269 * Board platform dat may be used to initialize regulators.
270 */
271struct tps65912_board {
272 int is_dcdc1_avs;
273 int is_dcdc2_avs;
274 int is_dcdc3_avs;
275 int is_dcdc4_avs;
276 int irq;
277 int irq_base;
278 int gpio_base;
279 struct regulator_init_data *tps65912_pmic_init_data;
280};
281
282/**
283 * struct tps65912 - tps65912 sub-driver chip access routines
284 */
285
286struct tps65912 {
287 struct device *dev;
288 /* for read/write acces */
289 struct mutex io_mutex;
290
291 /* For device IO interfaces: I2C or SPI */
292 void *control_data;
293
294 int (*read)(struct tps65912 *tps65912, u8 reg, int size, void *dest);
295 int (*write)(struct tps65912 *tps65912, u8 reg, int size, void *src);
296
297 /* Client devices */
298 struct tps65912_pmic *pmic;
299
300 /* GPIO Handling */
301 struct gpio_chip gpio;
302
303 /* IRQ Handling */
304 struct mutex irq_lock;
305 int chip_irq;
306 int irq_base;
307 int irq_num;
308 u32 irq_mask;
309};
310
311struct tps65912_platform_data {
312 int irq;
313 int irq_base;
314};
315
316unsigned int tps_chip(void);
317
318int tps65912_set_bits(struct tps65912 *tps65912, u8 reg, u8 mask);
319int tps65912_clear_bits(struct tps65912 *tps65912, u8 reg, u8 mask);
320int tps65912_reg_read(struct tps65912 *tps65912, u8 reg);
321int tps65912_reg_write(struct tps65912 *tps65912, u8 reg, u8 val);
322int tps65912_device_init(struct tps65912 *tps65912);
323void tps65912_device_exit(struct tps65912 *tps65912);
324int tps65912_irq_init(struct tps65912 *tps65912, int irq,
325 struct tps65912_platform_data *pdata);
326
327#endif /* __LINUX_MFD_TPS65912_H */
diff --git a/include/linux/mfd/twl4030-codec.h b/include/linux/mfd/twl4030-audio.h
index 5cc16bbd1da1..3d22b72df076 100644
--- a/include/linux/mfd/twl4030-codec.h
+++ b/include/linux/mfd/twl4030-audio.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * MFD driver for twl4030 codec submodule 2 * MFD driver for twl4030 audio submodule
3 * 3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5 * 5 *
@@ -259,14 +259,14 @@
259#define TWL4030_VIBRA_DIR_SEL 0x20 259#define TWL4030_VIBRA_DIR_SEL 0x20
260 260
261/* TWL4030 codec resource IDs */ 261/* TWL4030 codec resource IDs */
262enum twl4030_codec_res { 262enum twl4030_audio_res {
263 TWL4030_CODEC_RES_POWER = 0, 263 TWL4030_AUDIO_RES_POWER = 0,
264 TWL4030_CODEC_RES_APLL, 264 TWL4030_AUDIO_RES_APLL,
265 TWL4030_CODEC_RES_MAX, 265 TWL4030_AUDIO_RES_MAX,
266}; 266};
267 267
268int twl4030_codec_disable_resource(enum twl4030_codec_res id); 268int twl4030_audio_disable_resource(enum twl4030_audio_res id);
269int twl4030_codec_enable_resource(enum twl4030_codec_res id); 269int twl4030_audio_enable_resource(enum twl4030_audio_res id);
270unsigned int twl4030_codec_get_mclk(void); 270unsigned int twl4030_audio_get_mclk(void);
271 271
272#endif /* End of __TWL4030_CODEC_H__ */ 272#endif /* End of __TWL4030_CODEC_H__ */
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
new file mode 100644
index 000000000000..4c806f6d663e
--- /dev/null
+++ b/include/linux/mfd/twl6040.h
@@ -0,0 +1,228 @@
1/*
2 * MFD driver for twl6040
3 *
4 * Authors: Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
5 * Misael Lopez Cruz <misael.lopez@ti.com>
6 *
7 * Copyright: (C) 2011 Texas Instruments, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef __TWL6040_CODEC_H__
26#define __TWL6040_CODEC_H__
27
28#include <linux/interrupt.h>
29#include <linux/mfd/core.h>
30
31#define TWL6040_REG_ASICID 0x01
32#define TWL6040_REG_ASICREV 0x02
33#define TWL6040_REG_INTID 0x03
34#define TWL6040_REG_INTMR 0x04
35#define TWL6040_REG_NCPCTL 0x05
36#define TWL6040_REG_LDOCTL 0x06
37#define TWL6040_REG_HPPLLCTL 0x07
38#define TWL6040_REG_LPPLLCTL 0x08
39#define TWL6040_REG_LPPLLDIV 0x09
40#define TWL6040_REG_AMICBCTL 0x0A
41#define TWL6040_REG_DMICBCTL 0x0B
42#define TWL6040_REG_MICLCTL 0x0C
43#define TWL6040_REG_MICRCTL 0x0D
44#define TWL6040_REG_MICGAIN 0x0E
45#define TWL6040_REG_LINEGAIN 0x0F
46#define TWL6040_REG_HSLCTL 0x10
47#define TWL6040_REG_HSRCTL 0x11
48#define TWL6040_REG_HSGAIN 0x12
49#define TWL6040_REG_EARCTL 0x13
50#define TWL6040_REG_HFLCTL 0x14
51#define TWL6040_REG_HFLGAIN 0x15
52#define TWL6040_REG_HFRCTL 0x16
53#define TWL6040_REG_HFRGAIN 0x17
54#define TWL6040_REG_VIBCTLL 0x18
55#define TWL6040_REG_VIBDATL 0x19
56#define TWL6040_REG_VIBCTLR 0x1A
57#define TWL6040_REG_VIBDATR 0x1B
58#define TWL6040_REG_HKCTL1 0x1C
59#define TWL6040_REG_HKCTL2 0x1D
60#define TWL6040_REG_GPOCTL 0x1E
61#define TWL6040_REG_ALB 0x1F
62#define TWL6040_REG_DLB 0x20
63#define TWL6040_REG_TRIM1 0x28
64#define TWL6040_REG_TRIM2 0x29
65#define TWL6040_REG_TRIM3 0x2A
66#define TWL6040_REG_HSOTRIM 0x2B
67#define TWL6040_REG_HFOTRIM 0x2C
68#define TWL6040_REG_ACCCTL 0x2D
69#define TWL6040_REG_STATUS 0x2E
70
71#define TWL6040_CACHEREGNUM (TWL6040_REG_STATUS + 1)
72
73#define TWL6040_VIOREGNUM 18
74#define TWL6040_VDDREGNUM 21
75
76/* INTID (0x03) fields */
77
78#define TWL6040_THINT 0x01
79#define TWL6040_PLUGINT 0x02
80#define TWL6040_UNPLUGINT 0x04
81#define TWL6040_HOOKINT 0x08
82#define TWL6040_HFINT 0x10
83#define TWL6040_VIBINT 0x20
84#define TWL6040_READYINT 0x40
85
86/* INTMR (0x04) fields */
87
88#define TWL6040_THMSK 0x01
89#define TWL6040_PLUGMSK 0x02
90#define TWL6040_HOOKMSK 0x08
91#define TWL6040_HFMSK 0x10
92#define TWL6040_VIBMSK 0x20
93#define TWL6040_READYMSK 0x40
94#define TWL6040_ALLINT_MSK 0x7B
95
96/* NCPCTL (0x05) fields */
97
98#define TWL6040_NCPENA 0x01
99#define TWL6040_NCPOPEN 0x40
100
101/* LDOCTL (0x06) fields */
102
103#define TWL6040_LSLDOENA 0x01
104#define TWL6040_HSLDOENA 0x04
105#define TWL6040_REFENA 0x40
106#define TWL6040_OSCENA 0x80
107
108/* HPPLLCTL (0x07) fields */
109
110#define TWL6040_HPLLENA 0x01
111#define TWL6040_HPLLRST 0x02
112#define TWL6040_HPLLBP 0x04
113#define TWL6040_HPLLSQRENA 0x08
114#define TWL6040_MCLK_12000KHZ (0 << 5)
115#define TWL6040_MCLK_19200KHZ (1 << 5)
116#define TWL6040_MCLK_26000KHZ (2 << 5)
117#define TWL6040_MCLK_38400KHZ (3 << 5)
118#define TWL6040_MCLK_MSK 0x60
119
120/* LPPLLCTL (0x08) fields */
121
122#define TWL6040_LPLLENA 0x01
123#define TWL6040_LPLLRST 0x02
124#define TWL6040_LPLLSEL 0x04
125#define TWL6040_LPLLFIN 0x08
126#define TWL6040_HPLLSEL 0x10
127
128/* HSLCTL (0x10) fields */
129
130#define TWL6040_HSDACMODEL 0x02
131#define TWL6040_HSDRVMODEL 0x08
132
133/* HSRCTL (0x11) fields */
134
135#define TWL6040_HSDACMODER 0x02
136#define TWL6040_HSDRVMODER 0x08
137
138/* VIBCTLL (0x18) fields */
139
140#define TWL6040_VIBENAL 0x01
141#define TWL6040_VIBCTRLL 0x04
142#define TWL6040_VIBCTRLLP 0x08
143#define TWL6040_VIBCTRLLN 0x10
144
145/* VIBDATL (0x19) fields */
146
147#define TWL6040_VIBDAT_MAX 0x64
148
149/* VIBCTLR (0x1A) fields */
150
151#define TWL6040_VIBENAR 0x01
152#define TWL6040_VIBCTRLR 0x04
153#define TWL6040_VIBCTRLRP 0x08
154#define TWL6040_VIBCTRLRN 0x10
155
156/* GPOCTL (0x1E) fields */
157
158#define TWL6040_GPO1 0x01
159#define TWL6040_GPO2 0x02
160#define TWL6040_GPO3 0x03
161
162/* ACCCTL (0x2D) fields */
163
164#define TWL6040_I2CSEL 0x01
165#define TWL6040_RESETSPLIT 0x04
166#define TWL6040_INTCLRMODE 0x08
167
168/* STATUS (0x2E) fields */
169
170#define TWL6040_PLUGCOMP 0x02
171#define TWL6040_VIBLOCDET 0x10
172#define TWL6040_VIBROCDET 0x20
173#define TWL6040_TSHUTDET 0x40
174
175#define TWL6040_CELLS 2
176
177#define TWL6040_REV_ES1_0 0x00
178#define TWL6040_REV_ES1_1 0x01
179#define TWL6040_REV_ES1_2 0x02
180
181#define TWL6040_IRQ_TH 0
182#define TWL6040_IRQ_PLUG 1
183#define TWL6040_IRQ_HOOK 2
184#define TWL6040_IRQ_HF 3
185#define TWL6040_IRQ_VIB 4
186#define TWL6040_IRQ_READY 5
187
188/* PLL selection */
189#define TWL6040_SYSCLK_SEL_LPPLL 0
190#define TWL6040_SYSCLK_SEL_HPPLL 1
191
192struct twl6040 {
193 struct device *dev;
194 struct mutex mutex;
195 struct mutex io_mutex;
196 struct mutex irq_mutex;
197 struct mfd_cell cells[TWL6040_CELLS];
198 struct completion ready;
199
200 int audpwron;
201 int power_count;
202 int rev;
203
204 int pll;
205 unsigned int sysclk;
206
207 unsigned int irq;
208 unsigned int irq_base;
209 u8 irq_masks_cur;
210 u8 irq_masks_cache;
211};
212
213int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
214int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg,
215 u8 val);
216int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg,
217 u8 mask);
218int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg,
219 u8 mask);
220int twl6040_power(struct twl6040 *twl6040, int on);
221int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
222 unsigned int freq_in, unsigned int freq_out);
223int twl6040_get_pll(struct twl6040 *twl6040);
224unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
225int twl6040_irq_init(struct twl6040 *twl6040);
226void twl6040_irq_exit(struct twl6040 *twl6040);
227
228#endif /* End of __TWL6040_CODEC_H__ */
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 0d515ee1c247..8dda8ded5cda 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -17,6 +17,7 @@
17 17
18#include <linux/completion.h> 18#include <linux/completion.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/list.h>
20 21
21/* 22/*
22 * Register values. 23 * Register values.
@@ -234,9 +235,111 @@
234#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */ 235#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */
235#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */ 236#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */
236 237
238/*
239 * R16528 (0x4090) - Clock Control 1
240 */
241#define WM831X_CLKOUT_ENA 0x8000 /* CLKOUT_ENA */
242#define WM831X_CLKOUT_ENA_MASK 0x8000 /* CLKOUT_ENA */
243#define WM831X_CLKOUT_ENA_SHIFT 15 /* CLKOUT_ENA */
244#define WM831X_CLKOUT_ENA_WIDTH 1 /* CLKOUT_ENA */
245#define WM831X_CLKOUT_OD 0x2000 /* CLKOUT_OD */
246#define WM831X_CLKOUT_OD_MASK 0x2000 /* CLKOUT_OD */
247#define WM831X_CLKOUT_OD_SHIFT 13 /* CLKOUT_OD */
248#define WM831X_CLKOUT_OD_WIDTH 1 /* CLKOUT_OD */
249#define WM831X_CLKOUT_SLOT_MASK 0x0700 /* CLKOUT_SLOT - [10:8] */
250#define WM831X_CLKOUT_SLOT_SHIFT 8 /* CLKOUT_SLOT - [10:8] */
251#define WM831X_CLKOUT_SLOT_WIDTH 3 /* CLKOUT_SLOT - [10:8] */
252#define WM831X_CLKOUT_SLPSLOT_MASK 0x0070 /* CLKOUT_SLPSLOT - [6:4] */
253#define WM831X_CLKOUT_SLPSLOT_SHIFT 4 /* CLKOUT_SLPSLOT - [6:4] */
254#define WM831X_CLKOUT_SLPSLOT_WIDTH 3 /* CLKOUT_SLPSLOT - [6:4] */
255#define WM831X_CLKOUT_SRC 0x0001 /* CLKOUT_SRC */
256#define WM831X_CLKOUT_SRC_MASK 0x0001 /* CLKOUT_SRC */
257#define WM831X_CLKOUT_SRC_SHIFT 0 /* CLKOUT_SRC */
258#define WM831X_CLKOUT_SRC_WIDTH 1 /* CLKOUT_SRC */
259
260/*
261 * R16529 (0x4091) - Clock Control 2
262 */
263#define WM831X_XTAL_INH 0x8000 /* XTAL_INH */
264#define WM831X_XTAL_INH_MASK 0x8000 /* XTAL_INH */
265#define WM831X_XTAL_INH_SHIFT 15 /* XTAL_INH */
266#define WM831X_XTAL_INH_WIDTH 1 /* XTAL_INH */
267#define WM831X_XTAL_ENA 0x2000 /* XTAL_ENA */
268#define WM831X_XTAL_ENA_MASK 0x2000 /* XTAL_ENA */
269#define WM831X_XTAL_ENA_SHIFT 13 /* XTAL_ENA */
270#define WM831X_XTAL_ENA_WIDTH 1 /* XTAL_ENA */
271#define WM831X_XTAL_BKUPENA 0x1000 /* XTAL_BKUPENA */
272#define WM831X_XTAL_BKUPENA_MASK 0x1000 /* XTAL_BKUPENA */
273#define WM831X_XTAL_BKUPENA_SHIFT 12 /* XTAL_BKUPENA */
274#define WM831X_XTAL_BKUPENA_WIDTH 1 /* XTAL_BKUPENA */
275#define WM831X_FLL_AUTO 0x0080 /* FLL_AUTO */
276#define WM831X_FLL_AUTO_MASK 0x0080 /* FLL_AUTO */
277#define WM831X_FLL_AUTO_SHIFT 7 /* FLL_AUTO */
278#define WM831X_FLL_AUTO_WIDTH 1 /* FLL_AUTO */
279#define WM831X_FLL_AUTO_FREQ_MASK 0x0007 /* FLL_AUTO_FREQ - [2:0] */
280#define WM831X_FLL_AUTO_FREQ_SHIFT 0 /* FLL_AUTO_FREQ - [2:0] */
281#define WM831X_FLL_AUTO_FREQ_WIDTH 3 /* FLL_AUTO_FREQ - [2:0] */
282
283/*
284 * R16530 (0x4092) - FLL Control 1
285 */
286#define WM831X_FLL_FRAC 0x0004 /* FLL_FRAC */
287#define WM831X_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
288#define WM831X_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
289#define WM831X_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
290#define WM831X_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */
291#define WM831X_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */
292#define WM831X_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */
293#define WM831X_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
294#define WM831X_FLL_ENA 0x0001 /* FLL_ENA */
295#define WM831X_FLL_ENA_MASK 0x0001 /* FLL_ENA */
296#define WM831X_FLL_ENA_SHIFT 0 /* FLL_ENA */
297#define WM831X_FLL_ENA_WIDTH 1 /* FLL_ENA */
298
299/*
300 * R16531 (0x4093) - FLL Control 2
301 */
302#define WM831X_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
303#define WM831X_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
304#define WM831X_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
305#define WM831X_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
306#define WM831X_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
307#define WM831X_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
308#define WM831X_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
309#define WM831X_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
310#define WM831X_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
311
312/*
313 * R16532 (0x4094) - FLL Control 3
314 */
315#define WM831X_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
316#define WM831X_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
317#define WM831X_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
318
319/*
320 * R16533 (0x4095) - FLL Control 4
321 */
322#define WM831X_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
323#define WM831X_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
324#define WM831X_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
325#define WM831X_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
326#define WM831X_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
327#define WM831X_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
328
329/*
330 * R16534 (0x4096) - FLL Control 5
331 */
332#define WM831X_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
333#define WM831X_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
334#define WM831X_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
335#define WM831X_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
336#define WM831X_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
337#define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
338
237struct regulator_dev; 339struct regulator_dev;
238 340
239#define WM831X_NUM_IRQ_REGS 5 341#define WM831X_NUM_IRQ_REGS 5
342#define WM831X_NUM_GPIO_REGS 16
240 343
241enum wm831x_parent { 344enum wm831x_parent {
242 WM8310 = 0x8310, 345 WM8310 = 0x8310,
@@ -248,6 +351,12 @@ enum wm831x_parent {
248 WM8326 = 0x8326, 351 WM8326 = 0x8326,
249}; 352};
250 353
354struct wm831x;
355enum wm831x_auxadc;
356
357typedef int (*wm831x_auxadc_read_fn)(struct wm831x *wm831x,
358 enum wm831x_auxadc input);
359
251struct wm831x { 360struct wm831x {
252 struct mutex io_lock; 361 struct mutex io_lock;
253 362
@@ -261,7 +370,7 @@ struct wm831x {
261 370
262 int irq; /* Our chip IRQ */ 371 int irq; /* Our chip IRQ */
263 struct mutex irq_lock; 372 struct mutex irq_lock;
264 unsigned int irq_base; 373 int irq_base;
265 int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */ 374 int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
266 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ 375 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
267 376
@@ -272,8 +381,13 @@ struct wm831x {
272 381
273 int num_gpio; 382 int num_gpio;
274 383
384 /* Used by the interrupt controller code to post writes */
385 int gpio_update[WM831X_NUM_GPIO_REGS];
386
275 struct mutex auxadc_lock; 387 struct mutex auxadc_lock;
276 struct completion auxadc_done; 388 struct list_head auxadc_pending;
389 u16 auxadc_active;
390 wm831x_auxadc_read_fn auxadc_read;
277 391
278 /* The WM831x has a security key blocking access to certain 392 /* The WM831x has a security key blocking access to certain
279 * registers. The mutex is taken by the accessors for locking 393 * registers. The mutex is taken by the accessors for locking
@@ -300,5 +414,6 @@ void wm831x_device_exit(struct wm831x *wm831x);
300int wm831x_device_suspend(struct wm831x *wm831x); 414int wm831x_device_suspend(struct wm831x *wm831x);
301int wm831x_irq_init(struct wm831x *wm831x, int irq); 415int wm831x_irq_init(struct wm831x *wm831x, int irq);
302void wm831x_irq_exit(struct wm831x *wm831x); 416void wm831x_irq_exit(struct wm831x *wm831x);
417void wm831x_auxadc_init(struct wm831x *wm831x);
303 418
304#endif 419#endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
index ff42d700293f..0ba24599fe51 100644
--- a/include/linux/mfd/wm831x/pdata.h
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -120,6 +120,9 @@ struct wm831x_pdata {
120 /** Put the /IRQ line into CMOS mode */ 120 /** Put the /IRQ line into CMOS mode */
121 bool irq_cmos; 121 bool irq_cmos;
122 122
123 /** Disable the touchscreen */
124 bool disable_touch;
125
123 int irq_base; 126 int irq_base;
124 int gpio_base; 127 int gpio_base;
125 int gpio_defaults[WM831X_GPIO_NUM]; 128 int gpio_defaults[WM831X_GPIO_NUM];
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 00:32:44 -0400