diff options
author | Micky Ching <micky_ching@realsil.com.cn> | 2015-02-25 00:50:15 -0500 |
---|---|---|
committer | Lee Jones <lee.jones@linaro.org> | 2015-03-03 11:41:21 -0500 |
commit | 41bc2334737a32d3062a318dde5964590d0e24c9 (patch) | |
tree | 0167072cdea6c37af14527ce4fc19a4b6f298ea2 /include/linux/mfd/rtsx_pci.h | |
parent | 663c425f2c8d87a433629f09c5afd0af7e7e550c (diff) |
mfd: rtsx: Add support for rts525A
Add support for new chip rts525A.
Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'include/linux/mfd/rtsx_pci.h')
-rw-r--r-- | include/linux/mfd/rtsx_pci.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h index 754a18d4203a..ff843e7ca23d 100644 --- a/include/linux/mfd/rtsx_pci.h +++ b/include/linux/mfd/rtsx_pci.h | |||
@@ -727,6 +727,10 @@ | |||
727 | #define PHY_SSCCR3 0x03 | 727 | #define PHY_SSCCR3 0x03 |
728 | #define PHY_SSCCR3_STEP_IN 0x2740 | 728 | #define PHY_SSCCR3_STEP_IN 0x2740 |
729 | #define PHY_SSCCR3_CHECK_DELAY 0x0008 | 729 | #define PHY_SSCCR3_CHECK_DELAY 0x0008 |
730 | #define _PHY_ANA03 0x03 | ||
731 | #define _PHY_ANA03_TIMER_MAX 0x2700 | ||
732 | #define _PHY_ANA03_OOBS_DEB_EN 0x0040 | ||
733 | #define _PHY_CMU_DEBUG_EN 0x0008 | ||
730 | 734 | ||
731 | #define PHY_RTCR 0x04 | 735 | #define PHY_RTCR 0x04 |
732 | #define PHY_RDR 0x05 | 736 | #define PHY_RDR 0x05 |
@@ -785,6 +789,10 @@ | |||
785 | #define PHY_REV_STOP_CLKRD 0x0020 | 789 | #define PHY_REV_STOP_CLKRD 0x0020 |
786 | #define PHY_REV_RX_PWST 0x0008 | 790 | #define PHY_REV_RX_PWST 0x0008 |
787 | #define PHY_REV_STOP_CLKWR 0x0004 | 791 | #define PHY_REV_STOP_CLKWR 0x0004 |
792 | #define _PHY_REV0 0x19 | ||
793 | #define _PHY_REV0_FILTER_OUT 0x3800 | ||
794 | #define _PHY_REV0_CDR_BYPASS_PFD 0x0100 | ||
795 | #define _PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002 | ||
788 | 796 | ||
789 | #define PHY_FLD0 0x1A | 797 | #define PHY_FLD0 0x1A |
790 | #define PHY_ANA1A 0x1A | 798 | #define PHY_ANA1A 0x1A |
@@ -800,6 +808,13 @@ | |||
800 | #define PHY_FLD3_RXDELINK 0x0004 | 808 | #define PHY_FLD3_RXDELINK 0x0004 |
801 | #define PHY_ANA1D 0x1D | 809 | #define PHY_ANA1D 0x1D |
802 | #define PHY_ANA1D_DEBUG_ADDR 0x0004 | 810 | #define PHY_ANA1D_DEBUG_ADDR 0x0004 |
811 | #define _PHY_FLD0 0x1D | ||
812 | #define _PHY_FLD0_CLK_REQ_20C 0x8000 | ||
813 | #define _PHY_FLD0_RX_IDLE_EN 0x1000 | ||
814 | #define _PHY_FLD0_BIT_ERR_RSTN 0x0800 | ||
815 | #define _PHY_FLD0_BER_COUNT 0x01E0 | ||
816 | #define _PHY_FLD0_BER_TIMER 0x001E | ||
817 | #define _PHY_FLD0_CHECK_EN 0x0001 | ||
803 | 818 | ||
804 | #define PHY_FLD4 0x1E | 819 | #define PHY_FLD4 0x1E |
805 | #define PHY_FLD4_FLDEN_SEL 0x4000 | 820 | #define PHY_FLD4_FLDEN_SEL 0x4000 |