mfd: Add initial db8500 prcmu register access api

This patch adds an initial PRCMU register access API, which
for now should only be used for a very limited set of registers.

The idea about this API is that we split the PRCMU driver in
one part that deals with interaction with the PRCMU firmware
and one part that simply provide write accessors in the PRCMU
register range. The latter are just a collection of registers
exposed in the PRCMU register range for various purposes and
not related to the PRCMU firmware.

Currently we support some limited GPIO, SPI and UART settings
through this API.

Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

1 files changed, 122 insertions, 0 deletions

diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index 432a2d3fc198..b3b5adfa9e41 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -480,6 +480,30 @@ static inline int prcmu_stop_temp_sense(void)
                 return  db8500_prcmu_stop_temp_sense();
 }
 
+static inline u32 prcmu_read(unsigned int reg)
+{
+        if (cpu_is_u5500())
+                return -EINVAL;
+        else
+                return db8500_prcmu_read(reg);
+}
+
+static inline void prcmu_write(unsigned int reg, u32 value)
+{
+        if (cpu_is_u5500())
+                return;
+        else
+                db8500_prcmu_write(reg, value);
+}
+
+static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
+{
+        if (cpu_is_u5500())
+                return;
+        else
+                db8500_prcmu_write_masked(reg, mask, value);
+}
+
 static inline int prcmu_enable_a9wdog(u8 id)
 {
         if (cpu_is_u5500())
@@ -668,6 +692,104 @@ static inline int prcmu_stop_temp_sense(void)
         return 0;
 }
 
+static inline u32 prcmu_read(unsigned int reg)
+{
+        return 0;
+}
+
+static inline void prcmu_write(unsigned int reg, u32 value) {}
+
+static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
+
+#endif
+
+static inline void prcmu_set(unsigned int reg, u32 bits)
+{
+        prcmu_write_masked(reg, bits, bits);
+}
+
+static inline void prcmu_clear(unsigned int reg, u32 bits)
+{
+        prcmu_write_masked(reg, bits, 0);
+}
+
+#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
+
+/**
+ * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
+ */
+static inline void prcmu_enable_spi2(void)
+{
+        if (cpu_is_u8500())
+                prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
+}
+
+/**
+ * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
+ */
+static inline void prcmu_disable_spi2(void)
+{
+        if (cpu_is_u8500())
+                prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
+}
+
+/**
+ * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
+ * and UARTMOD on OtherAlternateC3.
+ */
+static inline void prcmu_enable_stm_mod_uart(void)
+{
+        if (cpu_is_u8500()) {
+                prcmu_set(DB8500_PRCM_GPIOCR,
+                        (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
+                         DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
+        }
+}
+
+/**
+ * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
+ * and UARTMOD on OtherAlternateC3.
+ */
+static inline void prcmu_disable_stm_mod_uart(void)
+{
+        if (cpu_is_u8500()) {
+                prcmu_clear(DB8500_PRCM_GPIOCR,
+                        (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
+                         DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
+        }
+}
+
+/**
+ * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
+ */
+static inline void prcmu_enable_stm_ape(void)
+{
+        if (cpu_is_u8500()) {
+                prcmu_set(DB8500_PRCM_GPIOCR,
+                        DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
+        }
+}
+
+/**
+ * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
+ */
+static inline void prcmu_disable_stm_ape(void)
+{
+        if (cpu_is_u8500()) {
+                prcmu_clear(DB8500_PRCM_GPIOCR,
+                        DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
+        }
+}
+
+#else
+
+static inline void prcmu_enable_spi2(void) {}
+static inline void prcmu_disable_spi2(void) {}
+static inline void prcmu_enable_stm_mod_uart(void) {}
+static inline void prcmu_disable_stm_mod_uart(void) {}
+static inline void prcmu_enable_stm_ape(void) {}
+static inline void prcmu_disable_stm_ape(void) {}
+
 #endif
 
 /* PRCMU QoS APE OPP class */