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authorBen Hutchings <bhutchings@solarflare.com>2009-05-15 02:04:12 -0400
committerDavid S. Miller <davem@davemloft.net>2009-05-18 00:03:42 -0400
commitf2a3e626202a87734a47153935ec9d15c7fcf761 (patch)
treef3111bbc6d57e3905ea9a75e87583df4a44d67ed /include/linux/mdio.h
parentdf18acca8eb13c8cf55fa45e9f9231dc51f64d98 (diff)
mdio: Add 10GBASE-T SNR register definition
These do not have an in-kernel user but may be useful to user-space. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/mdio.h')
-rw-r--r--include/linux/mdio.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/linux/mdio.h b/include/linux/mdio.h
index 26b4eb3bbee9..825f1e2e2ec3 100644
--- a/include/linux/mdio.h
+++ b/include/linux/mdio.h
@@ -46,6 +46,8 @@
46 46
47/* Media-dependent registers. */ 47/* Media-dependent registers. */
48#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ 48#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
49#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
50 * Lanes B-D are numbered 134-136. */
49#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */ 51#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
50#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */ 52#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
51#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */ 53#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
@@ -188,6 +190,11 @@
188/* PMA 10GBASE-T TX power register. */ 190/* PMA 10GBASE-T TX power register. */
189#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */ 191#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */
190 192
193/* PMA 10GBASE-T SNR registers. */
194/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
195#define MDIO_PMA_10GBT_SNR_BIAS 0x8000
196#define MDIO_PMA_10GBT_SNR_MAX 127
197
191/* PMA 10GBASE-R FEC ability register. */ 198/* PMA 10GBASE-R FEC ability register. */
192#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */ 199#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */
193#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */ 200#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */