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authorThomas Gleixner <tglx@linutronix.de>2011-02-08 11:28:12 -0500
committerThomas Gleixner <tglx@linutronix.de>2011-02-19 06:58:20 -0500
commit876dbd4cc1b35c1a4cb96a2be1d43ea0eabce3b4 (patch)
tree9be1e7e4cd4a4c9fadd98a9ac637020417215521 /include/linux/irq.h
parent2bdd10558c8d93009cb6c32ce9e30800fbb08add (diff)
genirq: Mirror irq trigger type bits in irq_data.state
That's the data structure chip functions get provided. Also allow them to signal the core code that they updated the flags in irq_data.state by returning IRQ_SET_MASK_OK_NOCOPY. The default is unchanged. The type bits should be accessed via: val = irqd_get_trigger_type(irqdata); and irqd_set_trigger_type(irqdata, val); Coders who access them directly will be tracked down and slapped with stinking trouts. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/linux/irq.h')
-rw-r--r--include/linux/irq.h26
1 files changed, 25 insertions, 1 deletions
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 8da1782ecfca..be73c0a3c19d 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -46,7 +46,9 @@ typedef void (*irq_flow_handler_t)(unsigned int irq,
46#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 46#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
47#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ 47#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
48#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ 48#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
49#define IRQ_TYPE_LEVEL_MASK (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)
49#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ 50#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
51
50#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ 52#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
51 53
52/* Internal flags */ 54/* Internal flags */
@@ -131,17 +133,20 @@ struct irq_data {
131/* 133/*
132 * Bit masks for irq_data.state 134 * Bit masks for irq_data.state
133 * 135 *
136 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
134 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 137 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
135 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 138 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
136 * IRQD_PER_CPU - Interrupt is per cpu 139 * IRQD_PER_CPU - Interrupt is per cpu
137 * IRQD_AFFINITY_SET - Interrupt affinity was set 140 * IRQD_AFFINITY_SET - Interrupt affinity was set
141 * IRQD_LEVEL - Interrupt is level triggered
138 */ 142 */
139enum { 143enum {
140 /* Bit 0 - 7 reserved for TYPE will use later */ 144 IRQD_TRIGGER_MASK = 0xf,
141 IRQD_SETAFFINITY_PENDING = (1 << 8), 145 IRQD_SETAFFINITY_PENDING = (1 << 8),
142 IRQD_NO_BALANCING = (1 << 10), 146 IRQD_NO_BALANCING = (1 << 10),
143 IRQD_PER_CPU = (1 << 11), 147 IRQD_PER_CPU = (1 << 11),
144 IRQD_AFFINITY_SET = (1 << 12), 148 IRQD_AFFINITY_SET = (1 << 12),
149 IRQD_LEVEL = (1 << 13),
145}; 150};
146 151
147static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 152static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
@@ -164,6 +169,25 @@ static inline bool irqd_affinity_was_set(struct irq_data *d)
164 return d->state_use_accessors & IRQD_AFFINITY_SET; 169 return d->state_use_accessors & IRQD_AFFINITY_SET;
165} 170}
166 171
172static inline u32 irqd_get_trigger_type(struct irq_data *d)
173{
174 return d->state_use_accessors & IRQD_TRIGGER_MASK;
175}
176
177/*
178 * Must only be called inside irq_chip.irq_set_type() functions.
179 */
180static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
181{
182 d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
183 d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
184}
185
186static inline bool irqd_is_level_type(struct irq_data *d)
187{
188 return d->state_use_accessors & IRQD_LEVEL;
189}
190
167/** 191/**
168 * struct irq_chip - hardware interrupt chip descriptor 192 * struct irq_chip - hardware interrupt chip descriptor
169 * 193 *