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authorFenghua Yu <fenghua.yu@intel.com>2009-04-24 20:30:20 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2009-04-29 01:54:34 -0400
commit4ed0d3e6c64cfd9ba4ceb2099b10d1cf8ece4320 (patch)
tree950bacfaf57040aafbcc2ea9b52eb171d35c23bd /include/linux/intel-iommu.h
parent091069740304c979f957ceacec39c461d0192158 (diff)
Intel IOMMU Pass Through Support
The patch adds kernel parameter intel_iommu=pt to set up pass through mode in context mapping entry. This disables DMAR in linux kernel; but KVM still runs on VT-d and interrupt remapping still works. In this mode, kernel uses swiotlb for DMA API functions but other VT-d functionalities are enabled for KVM. KVM always uses multi level translation page table in VT-d. By default, pass though mode is disabled in kernel. This is useful when people don't want to enable VT-d DMAR in kernel but still want to use KVM and interrupt remapping for reasons like DMAR performance concern or debug purpose. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Acked-by: Weidong Han <weidong@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'include/linux/intel-iommu.h')
-rw-r--r--include/linux/intel-iommu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index aa8c53171233..7246971a7feb 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -120,6 +120,7 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
120 (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16) 120 (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
121#define ecap_coherent(e) ((e) & 0x1) 121#define ecap_coherent(e) ((e) & 0x1)
122#define ecap_qis(e) ((e) & 0x2) 122#define ecap_qis(e) ((e) & 0x2)
123#define ecap_pass_through(e) ((e >> 6) & 0x1)
123#define ecap_eim_support(e) ((e >> 4) & 0x1) 124#define ecap_eim_support(e) ((e >> 4) & 0x1)
124#define ecap_ir_support(e) ((e >> 3) & 0x1) 125#define ecap_ir_support(e) ((e >> 3) & 0x1)
125#define ecap_max_handle_mask(e) ((e >> 20) & 0xf) 126#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
@@ -302,6 +303,7 @@ struct intel_iommu {
302 spinlock_t register_lock; /* protect register handling */ 303 spinlock_t register_lock; /* protect register handling */
303 int seq_id; /* sequence id of the iommu */ 304 int seq_id; /* sequence id of the iommu */
304 int agaw; /* agaw of this iommu */ 305 int agaw; /* agaw of this iommu */
306 int msagaw; /* max sagaw of this iommu */
305 unsigned int irq; 307 unsigned int irq;
306 unsigned char name[13]; /* Device Name */ 308 unsigned char name[13]; /* Device Name */
307 309