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authorIngo Molnar <mingo@elte.hu>2009-04-07 06:05:21 -0400
committerIngo Molnar <mingo@elte.hu>2009-04-07 06:05:25 -0400
commit6c009ecef8cca28c7c09eb16d0802e37915a76e1 (patch)
tree11c773f780186fdb9fbc9c80a73fb7c8426b1fba /include/linux/intel-iommu.h
parent98c2aaf8be5baf7193be37fb28bce8e7327158bc (diff)
parentd508afb437daee7cf07da085b635c44a4ebf9b38 (diff)
Merge branch 'linus' into perfcounters/core
Merge reason: need the upstream facility added by: 7f1e2ca: hrtimer: fix rq->lock inversion (again) Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/linux/intel-iommu.h')
-rw-r--r--include/linux/intel-iommu.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 77214ead1a36..aa8c53171233 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -164,6 +164,7 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
164#define DMA_GCMD_QIE (((u32)1) << 26) 164#define DMA_GCMD_QIE (((u32)1) << 26)
165#define DMA_GCMD_SIRTP (((u32)1) << 24) 165#define DMA_GCMD_SIRTP (((u32)1) << 24)
166#define DMA_GCMD_IRE (((u32) 1) << 25) 166#define DMA_GCMD_IRE (((u32) 1) << 25)
167#define DMA_GCMD_CFI (((u32) 1) << 23)
167 168
168/* GSTS_REG */ 169/* GSTS_REG */
169#define DMA_GSTS_TES (((u32)1) << 31) 170#define DMA_GSTS_TES (((u32)1) << 31)
@@ -174,6 +175,7 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
174#define DMA_GSTS_QIES (((u32)1) << 26) 175#define DMA_GSTS_QIES (((u32)1) << 26)
175#define DMA_GSTS_IRTPS (((u32)1) << 24) 176#define DMA_GSTS_IRTPS (((u32)1) << 24)
176#define DMA_GSTS_IRES (((u32)1) << 25) 177#define DMA_GSTS_IRES (((u32)1) << 25)
178#define DMA_GSTS_CFIS (((u32)1) << 23)
177 179
178/* CCMD_REG */ 180/* CCMD_REG */
179#define DMA_CCMD_ICC (((u64)1) << 63) 181#define DMA_CCMD_ICC (((u64)1) << 63)
@@ -284,6 +286,14 @@ struct iommu_flush {
284 unsigned int size_order, u64 type, int non_present_entry_flush); 286 unsigned int size_order, u64 type, int non_present_entry_flush);
285}; 287};
286 288
289enum {
290 SR_DMAR_FECTL_REG,
291 SR_DMAR_FEDATA_REG,
292 SR_DMAR_FEADDR_REG,
293 SR_DMAR_FEUADDR_REG,
294 MAX_SR_DMAR_REGS
295};
296
287struct intel_iommu { 297struct intel_iommu {
288 void __iomem *reg; /* Pointer to hardware regs, virtual addr */ 298 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
289 u64 cap; 299 u64 cap;
@@ -304,6 +314,8 @@ struct intel_iommu {
304 struct iommu_flush flush; 314 struct iommu_flush flush;
305#endif 315#endif
306 struct q_inval *qi; /* Queued invalidation info */ 316 struct q_inval *qi; /* Queued invalidation info */
317 u32 *iommu_state; /* Store iommu states between suspend and resume.*/
318
307#ifdef CONFIG_INTR_REMAP 319#ifdef CONFIG_INTR_REMAP
308 struct ir_table *ir_table; /* Interrupt remapping info */ 320 struct ir_table *ir_table; /* Interrupt remapping info */
309#endif 321#endif
@@ -322,6 +334,7 @@ extern int alloc_iommu(struct dmar_drhd_unit *drhd);
322extern void free_iommu(struct intel_iommu *iommu); 334extern void free_iommu(struct intel_iommu *iommu);
323extern int dmar_enable_qi(struct intel_iommu *iommu); 335extern int dmar_enable_qi(struct intel_iommu *iommu);
324extern void dmar_disable_qi(struct intel_iommu *iommu); 336extern void dmar_disable_qi(struct intel_iommu *iommu);
337extern int dmar_reenable_qi(struct intel_iommu *iommu);
325extern void qi_global_iec(struct intel_iommu *iommu); 338extern void qi_global_iec(struct intel_iommu *iommu);
326 339
327extern int qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, 340extern int qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,