diff options
author | Kumar Gala <galak@freescale.com> | 2005-06-21 20:15:18 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-06-21 21:46:23 -0400 |
commit | 5b37b700f7c491a9320f4e29472bbaf23dded8fd (patch) | |
tree | e8a77c322bec5e75f0524c99f3be61645560b3c3 /include/linux/fsl_devices.h | |
parent | da3caa204ca40c32dcb751ebead2a6835b83e8d1 (diff) |
[PATCH] ppc32: Added support for new MPC8548 family of PowerQUICC III processors
Added descriptions of the new MPC8548 family processors, e500 core and
peripherals.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/linux/fsl_devices.h')
-rw-r--r-- | include/linux/fsl_devices.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index faaff4c64559..70f54af87b9f 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h | |||
@@ -51,6 +51,7 @@ struct gianfar_platform_data { | |||
51 | 51 | ||
52 | /* board specific information */ | 52 | /* board specific information */ |
53 | u32 board_flags; | 53 | u32 board_flags; |
54 | u32 phy_flags; | ||
54 | u32 phyid; | 55 | u32 phyid; |
55 | u32 interruptPHY; | 56 | u32 interruptPHY; |
56 | u8 mac_addr[6]; | 57 | u8 mac_addr[6]; |
@@ -61,9 +62,14 @@ struct gianfar_platform_data { | |||
61 | #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 | 62 | #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 |
62 | #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004 | 63 | #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004 |
63 | #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008 | 64 | #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008 |
65 | #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010 | ||
66 | #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020 | ||
67 | #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040 | ||
68 | #define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080 | ||
64 | 69 | ||
65 | /* Flags in gianfar_platform_data */ | 70 | /* Flags in gianfar_platform_data */ |
66 | #define FSL_GIANFAR_BRD_HAS_PHY_INTR 0x00000001 /* if not set use a timer */ | 71 | #define FSL_GIANFAR_BRD_HAS_PHY_INTR 0x00000001 /* set or use a timer */ |
72 | #define FSL_GIANFAR_BRD_IS_REDUCED 0x00000002 /* Set if RGMII, RMII */ | ||
67 | 73 | ||
68 | struct fsl_i2c_platform_data { | 74 | struct fsl_i2c_platform_data { |
69 | /* device specific information */ | 75 | /* device specific information */ |