diff options
author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-02-03 11:17:48 -0500 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-03-21 14:19:50 -0400 |
commit | 01a6e28b5096aea6801a21bdc20bf1de32833af5 (patch) | |
tree | d1cb324e0ba1173806ae16e1fbc18439b1f1d08b /include/linux/edac.h | |
parent | b877763ea01d740f6c62a35c45b7351fec9c288d (diff) |
edac: Improve the comments to better describe the memory concepts
The Computer memory terminology has changed with time since EDAC was
originally written: new concepts were introduced, and some things have
different meanings, depending on the memory architecture.
Improve the definition of all related terms.
Also, describe each memory type in a more detailed fashion.
No functional changes. Just comments were touched.
Acked-by: Borislav Petkov <borislav.petkov@amd.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'include/linux/edac.h')
-rw-r--r-- | include/linux/edac.h | 157 |
1 files changed, 111 insertions, 46 deletions
diff --git a/include/linux/edac.h b/include/linux/edac.h index 1cd3947987e5..0714d67a6e1a 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h | |||
@@ -66,25 +66,64 @@ enum dev_type { | |||
66 | #define DEV_FLAG_X32 BIT(DEV_X32) | 66 | #define DEV_FLAG_X32 BIT(DEV_X32) |
67 | #define DEV_FLAG_X64 BIT(DEV_X64) | 67 | #define DEV_FLAG_X64 BIT(DEV_X64) |
68 | 68 | ||
69 | /* memory types */ | 69 | /** |
70 | * enum mem_type - memory types. For a more detailed reference, please see | ||
71 | * http://en.wikipedia.org/wiki/DRAM | ||
72 | * | ||
73 | * @MEM_EMPTY Empty csrow | ||
74 | * @MEM_RESERVED: Reserved csrow type | ||
75 | * @MEM_UNKNOWN: Unknown csrow type | ||
76 | * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995. | ||
77 | * @MEM_EDO: EDO - Extended data out, used on systems up to 1998. | ||
78 | * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant. | ||
79 | * @MEM_SDR: SDR - Single data rate SDRAM | ||
80 | * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory | ||
81 | * They use 3 pins for chip select: Pins 0 and 2 are | ||
82 | * for rank 0; pins 1 and 3 are for rank 1, if the memory | ||
83 | * is dual-rank. | ||
84 | * @MEM_RDR: Registered SDR SDRAM | ||
85 | * @MEM_DDR: Double data rate SDRAM | ||
86 | * http://en.wikipedia.org/wiki/DDR_SDRAM | ||
87 | * @MEM_RDDR: Registered Double data rate SDRAM | ||
88 | * This is a variant of the DDR memories. | ||
89 | * A registered memory has a buffer inside it, hiding | ||
90 | * part of the memory details to the memory controller. | ||
91 | * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers. | ||
92 | * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F. | ||
93 | * Those memories are labed as "PC2-" instead of "PC" to | ||
94 | * differenciate from DDR. | ||
95 | * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205 | ||
96 | * and JESD206. | ||
97 | * Those memories are accessed per DIMM slot, and not by | ||
98 | * a chip select signal. | ||
99 | * @MEM_RDDR2: Registered DDR2 RAM | ||
100 | * This is a variant of the DDR2 memories. | ||
101 | * @MEM_XDR: Rambus XDR | ||
102 | * It is an evolution of the original RAMBUS memories, | ||
103 | * created to compete with DDR2. Weren't used on any | ||
104 | * x86 arch, but cell_edac PPC memory controller uses it. | ||
105 | * @MEM_DDR3: DDR3 RAM | ||
106 | * @MEM_RDDR3: Registered DDR3 RAM | ||
107 | * This is a variant of the DDR3 memories. | ||
108 | */ | ||
70 | enum mem_type { | 109 | enum mem_type { |
71 | MEM_EMPTY = 0, /* Empty csrow */ | 110 | MEM_EMPTY = 0, |
72 | MEM_RESERVED, /* Reserved csrow type */ | 111 | MEM_RESERVED, |
73 | MEM_UNKNOWN, /* Unknown csrow type */ | 112 | MEM_UNKNOWN, |
74 | MEM_FPM, /* Fast page mode */ | 113 | MEM_FPM, |
75 | MEM_EDO, /* Extended data out */ | 114 | MEM_EDO, |
76 | MEM_BEDO, /* Burst Extended data out */ | 115 | MEM_BEDO, |
77 | MEM_SDR, /* Single data rate SDRAM */ | 116 | MEM_SDR, |
78 | MEM_RDR, /* Registered single data rate SDRAM */ | 117 | MEM_RDR, |
79 | MEM_DDR, /* Double data rate SDRAM */ | 118 | MEM_DDR, |
80 | MEM_RDDR, /* Registered Double data rate SDRAM */ | 119 | MEM_RDDR, |
81 | MEM_RMBS, /* Rambus DRAM */ | 120 | MEM_RMBS, |
82 | MEM_DDR2, /* DDR2 RAM */ | 121 | MEM_DDR2, |
83 | MEM_FB_DDR2, /* fully buffered DDR2 */ | 122 | MEM_FB_DDR2, |
84 | MEM_RDDR2, /* Registered DDR2 RAM */ | 123 | MEM_RDDR2, |
85 | MEM_XDR, /* Rambus XDR */ | 124 | MEM_XDR, |
86 | MEM_DDR3, /* DDR3 RAM */ | 125 | MEM_DDR3, |
87 | MEM_RDDR3, /* Registered DDR3 RAM */ | 126 | MEM_RDDR3, |
88 | }; | 127 | }; |
89 | 128 | ||
90 | #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) | 129 | #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) |
@@ -162,8 +201,9 @@ enum scrub_type { | |||
162 | #define OP_OFFLINE 0x300 | 201 | #define OP_OFFLINE 0x300 |
163 | 202 | ||
164 | /* | 203 | /* |
165 | * There are several things to be aware of that aren't at all obvious: | 204 | * Concepts used at the EDAC subsystem |
166 | * | 205 | * |
206 | * There are several things to be aware of that aren't at all obvious: | ||
167 | * | 207 | * |
168 | * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc.. | 208 | * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc.. |
169 | * | 209 | * |
@@ -172,36 +212,61 @@ enum scrub_type { | |||
172 | * creating a common ground for discussion, terms and their definitions | 212 | * creating a common ground for discussion, terms and their definitions |
173 | * will be established. | 213 | * will be established. |
174 | * | 214 | * |
175 | * Memory devices: The individual chip on a memory stick. These devices | 215 | * Memory devices: The individual DRAM chips on a memory stick. These |
176 | * commonly output 4 and 8 bits each. Grouping several | 216 | * devices commonly output 4 and 8 bits each (x4, x8). |
177 | * of these in parallel provides 64 bits which is common | 217 | * Grouping several of these in parallel provides the |
178 | * for a memory stick. | 218 | * number of bits that the memory controller expects: |
219 | * typically 72 bits, in order to provide 64 bits + | ||
220 | * 8 bits of ECC data. | ||
179 | * | 221 | * |
180 | * Memory Stick: A printed circuit board that aggregates multiple | 222 | * Memory Stick: A printed circuit board that aggregates multiple |
181 | * memory devices in parallel. This is the atomic | 223 | * memory devices in parallel. In general, this is the |
182 | * memory component that is purchaseable by Joe consumer | 224 | * Field Replaceable Unit (FRU) which gets replaced, in |
183 | * and loaded into a memory socket. | 225 | * the case of excessive errors. Most often it is also |
226 | * called DIMM (Dual Inline Memory Module). | ||
184 | * | 227 | * |
185 | * Socket: A physical connector on the motherboard that accepts | 228 | * Memory Socket: A physical connector on the motherboard that accepts |
186 | * a single memory stick. | 229 | * a single memory stick. Also called as "slot" on several |
230 | * datasheets. | ||
187 | * | 231 | * |
188 | * Channel: Set of memory devices on a memory stick that must be | 232 | * Channel: A memory controller channel, responsible to communicate |
189 | * grouped in parallel with one or more additional | 233 | * with a group of DIMMs. Each channel has its own |
190 | * channels from other memory sticks. This parallel | 234 | * independent control (command) and data bus, and can |
191 | * grouping of the output from multiple channels are | 235 | * be used independently or grouped with other channels. |
192 | * necessary for the smallest granularity of memory access. | ||
193 | * Some memory controllers are capable of single channel - | ||
194 | * which means that memory sticks can be loaded | ||
195 | * individually. Other memory controllers are only | ||
196 | * capable of dual channel - which means that memory | ||
197 | * sticks must be loaded as pairs (see "socket set"). | ||
198 | * | 236 | * |
199 | * Chip-select row: All of the memory devices that are selected together. | 237 | * Branch: It is typically the highest hierarchy on a |
200 | * for a single, minimum grain of memory access. | 238 | * Fully-Buffered DIMM memory controller. |
201 | * This selects all of the parallel memory devices across | 239 | * Typically, it contains two channels. |
202 | * all of the parallel channels. Common chip-select rows | 240 | * Two channels at the same branch can be used in single |
203 | * for single channel are 64 bits, for dual channel 128 | 241 | * mode or in lockstep mode. |
204 | * bits. | 242 | * When lockstep is enabled, the cacheline is doubled, |
243 | * but it generally brings some performance penalty. | ||
244 | * Also, it is generally not possible to point to just one | ||
245 | * memory stick when an error occurs, as the error | ||
246 | * correction code is calculated using two DIMMs instead | ||
247 | * of one. Due to that, it is capable of correcting more | ||
248 | * errors than on single mode. | ||
249 | * | ||
250 | * Single-channel: The data accessed by the memory controller is contained | ||
251 | * into one dimm only. E. g. if the data is 64 bits-wide, | ||
252 | * the data flows to the CPU using one 64 bits parallel | ||
253 | * access. | ||
254 | * Typically used with SDR, DDR, DDR2 and DDR3 memories. | ||
255 | * FB-DIMM and RAMBUS use a different concept for channel, | ||
256 | * so this concept doesn't apply there. | ||
257 | * | ||
258 | * Double-channel: The data size accessed by the memory controller is | ||
259 | * interlaced into two dimms, accessed at the same time. | ||
260 | * E. g. if the DIMM is 64 bits-wide (72 bits with ECC), | ||
261 | * the data flows to the CPU using a 128 bits parallel | ||
262 | * access. | ||
263 | * | ||
264 | * Chip-select row: This is the name of the DRAM signal used to select the | ||
265 | * DRAM ranks to be accessed. Common chip-select rows for | ||
266 | * single channel are 64 bits, for dual channel 128 bits. | ||
267 | * It may not be visible by the memory controller, as some | ||
268 | * DIMM types have a memory buffer that can hide direct | ||
269 | * access to it from the Memory Controller. | ||
205 | * | 270 | * |
206 | * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory. | 271 | * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory. |
207 | * Motherboards commonly drive two chip-select pins to | 272 | * Motherboards commonly drive two chip-select pins to |
@@ -214,8 +279,8 @@ enum scrub_type { | |||
214 | * | 279 | * |
215 | * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick. | 280 | * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick. |
216 | * A double-sided stick has two chip-select rows which | 281 | * A double-sided stick has two chip-select rows which |
217 | * access different sets of memory devices. The two | 282 | * access different sets of memory devices. The two |
218 | * rows cannot be accessed concurrently. "Double-sided" | 283 | * rows cannot be accessed concurrently. "Double-sided" |
219 | * is irrespective of the memory devices being mounted | 284 | * is irrespective of the memory devices being mounted |
220 | * on both sides of the memory stick. | 285 | * on both sides of the memory stick. |
221 | * | 286 | * |