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authorViresh Kumar <viresh.kumar@st.com>2012-02-01 05:42:28 -0500
committerVinod Koul <vinod.koul@linux.intel.com>2012-02-22 07:45:39 -0500
commita1c46016794fdd83b7993303915ec7f4a06682b7 (patch)
tree92b11c6c5e156025eacdc11110e4d8f15f3c8b13 /include/linux/dw_dmac.h
parente2b35f3dbfc080f15b72834d08f04f0269dbe9be (diff)
dmaengine/dw_dmac: Remove unused fields in struct dw_dma_slave
Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
Diffstat (limited to 'include/linux/dw_dmac.h')
-rw-r--r--include/linux/dw_dmac.h38
1 files changed, 0 insertions, 38 deletions
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
index f2c64f92c4a0..2412e02d7c0f 100644
--- a/include/linux/dw_dmac.h
+++ b/include/linux/dw_dmac.h
@@ -31,18 +31,6 @@ struct dw_dma_platform_data {
31 unsigned char chan_priority; 31 unsigned char chan_priority;
32}; 32};
33 33
34/**
35 * enum dw_dma_slave_width - DMA slave register access width.
36 * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
37 * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
38 * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
39 */
40enum dw_dma_slave_width {
41 DW_DMA_SLAVE_WIDTH_8BIT,
42 DW_DMA_SLAVE_WIDTH_16BIT,
43 DW_DMA_SLAVE_WIDTH_32BIT,
44};
45
46/* bursts size */ 34/* bursts size */
47enum dw_dma_msize { 35enum dw_dma_msize {
48 DW_DMA_MSIZE_1, 36 DW_DMA_MSIZE_1,
@@ -55,47 +43,21 @@ enum dw_dma_msize {
55 DW_DMA_MSIZE_256, 43 DW_DMA_MSIZE_256,
56}; 44};
57 45
58/* flow controller */
59enum dw_dma_fc {
60 DW_DMA_FC_D_M2M,
61 DW_DMA_FC_D_M2P,
62 DW_DMA_FC_D_P2M,
63 DW_DMA_FC_D_P2P,
64 DW_DMA_FC_P_P2M,
65 DW_DMA_FC_SP_P2P,
66 DW_DMA_FC_P_M2P,
67 DW_DMA_FC_DP_P2P,
68};
69
70/** 46/**
71 * struct dw_dma_slave - Controller-specific information about a slave 47 * struct dw_dma_slave - Controller-specific information about a slave
72 * 48 *
73 * @dma_dev: required DMA master device 49 * @dma_dev: required DMA master device
74 * @tx_reg: physical address of data register used for
75 * memory-to-peripheral transfers
76 * @rx_reg: physical address of data register used for
77 * peripheral-to-memory transfers
78 * @reg_width: peripheral register width
79 * @cfg_hi: Platform-specific initializer for the CFG_HI register 50 * @cfg_hi: Platform-specific initializer for the CFG_HI register
80 * @cfg_lo: Platform-specific initializer for the CFG_LO register 51 * @cfg_lo: Platform-specific initializer for the CFG_LO register
81 * @src_master: src master for transfers on allocated channel. 52 * @src_master: src master for transfers on allocated channel.
82 * @dst_master: dest master for transfers on allocated channel. 53 * @dst_master: dest master for transfers on allocated channel.
83 * @src_msize: src burst size.
84 * @dst_msize: dest burst size.
85 * @fc: flow controller for DMA transfer
86 */ 54 */
87struct dw_dma_slave { 55struct dw_dma_slave {
88 struct device *dma_dev; 56 struct device *dma_dev;
89 dma_addr_t tx_reg;
90 dma_addr_t rx_reg;
91 enum dw_dma_slave_width reg_width;
92 u32 cfg_hi; 57 u32 cfg_hi;
93 u32 cfg_lo; 58 u32 cfg_lo;
94 u8 src_master; 59 u8 src_master;
95 u8 dst_master; 60 u8 dst_master;
96 u8 src_msize;
97 u8 dst_msize;
98 u8 fc;
99}; 61};
100 62
101/* Platform-configurable bits in CFG_HI */ 63/* Platform-configurable bits in CFG_HI */