diff options
author | Viresh Kumar <viresh.kumar@st.com> | 2011-03-03 05:17:22 -0500 |
---|---|---|
committer | Vinod Koul <vinod.koul@intel.com> | 2011-03-06 14:42:28 -0500 |
commit | 93317e8e35b77633d589fe0e132291195757d785 (patch) | |
tree | c3419c1a02e3952506ca0af281f9f9c5bc52888d /include/linux/dw_dmac.h | |
parent | b0c3130d69bda5cd91aa3b3f08e7878df49fde69 (diff) |
dw_dmac: Pass Channel Priority from platform_data
In Synopsys designware, channel priority is programmable. This patch adds
support for passing channel priority through platform data. By default Ascending
channel priority will be followed, i.e. channel 0 will get highest priority and
channel 7 will get lowest.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'include/linux/dw_dmac.h')
-rw-r--r-- | include/linux/dw_dmac.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h index a18c498984d9..64c76da571ef 100644 --- a/include/linux/dw_dmac.h +++ b/include/linux/dw_dmac.h | |||
@@ -25,6 +25,9 @@ struct dw_dma_platform_data { | |||
25 | #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ | 25 | #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ |
26 | #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ | 26 | #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ |
27 | unsigned char chan_allocation_order; | 27 | unsigned char chan_allocation_order; |
28 | #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ | ||
29 | #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ | ||
30 | unsigned char chan_priority; | ||
28 | }; | 31 | }; |
29 | 32 | ||
30 | /** | 33 | /** |
@@ -70,7 +73,6 @@ struct dw_dma_slave { | |||
70 | #define DWC_CFGH_DST_PER(x) ((x) << 11) | 73 | #define DWC_CFGH_DST_PER(x) ((x) << 11) |
71 | 74 | ||
72 | /* Platform-configurable bits in CFG_LO */ | 75 | /* Platform-configurable bits in CFG_LO */ |
73 | #define DWC_CFGL_PRIO(x) ((x) << 5) /* priority */ | ||
74 | #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ | 76 | #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ |
75 | #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) | 77 | #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) |
76 | #define DWC_CFGL_LOCK_CH_XACT (2 << 12) | 78 | #define DWC_CFGL_LOCK_CH_XACT (2 << 12) |