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author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-23 15:03:18 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-23 15:03:18 -0400 |
commit | 5554b35933245e95710d709175e14c02cbc956a4 (patch) | |
tree | 2eeb2f05a7061da3c9a3bc9ea69a344b990c6b49 /include/linux/dw_dmac.h | |
parent | 0f6e38a6381446eff5175b77d1094834a633a90f (diff) | |
parent | 7f1b358a236ee9c19657a619ac6f2dcabcaa0924 (diff) |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (24 commits)
I/OAT: I/OAT version 3.0 support
I/OAT: tcp_dma_copybreak default value dependent on I/OAT version
I/OAT: Add watchdog/reset functionality to ioatdma
iop_adma: cleanup iop_chan_xor_slot_count
iop_adma: document how to calculate the minimum descriptor pool size
iop_adma: directly reclaim descriptors on allocation failure
async_tx: make async_tx_test_ack a boolean routine
async_tx: remove depend_tx from async_tx_sync_epilog
async_tx: export async_tx_quiesce
async_tx: fix handling of the "out of descriptor" condition in async_xor
async_tx: ensure the xor destination buffer remains dma-mapped
async_tx: list_for_each_entry_rcu() cleanup
dmaengine: Driver for the Synopsys DesignWare DMA controller
dmaengine: Add slave DMA interface
dmaengine: add DMA_COMPL_SKIP_{SRC,DEST}_UNMAP flags to control dma unmap
dmaengine: Add dma_client parameter to device_alloc_chan_resources
dmatest: Simple DMA memcpy test client
dmaengine: DMA engine driver for Marvell XOR engine
iop-adma: fix platform driver hotplug/coldplug
dmaengine: track the number of clients using a channel
...
Fixed up conflict in drivers/dca/dca-sysfs.c manually
Diffstat (limited to 'include/linux/dw_dmac.h')
-rw-r--r-- | include/linux/dw_dmac.h | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h new file mode 100644 index 000000000000..04d217b442bf --- /dev/null +++ b/include/linux/dw_dmac.h | |||
@@ -0,0 +1,62 @@ | |||
1 | /* | ||
2 | * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on | ||
3 | * AVR32 systems.) | ||
4 | * | ||
5 | * Copyright (C) 2007 Atmel Corporation | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | #ifndef DW_DMAC_H | ||
12 | #define DW_DMAC_H | ||
13 | |||
14 | #include <linux/dmaengine.h> | ||
15 | |||
16 | /** | ||
17 | * struct dw_dma_platform_data - Controller configuration parameters | ||
18 | * @nr_channels: Number of channels supported by hardware (max 8) | ||
19 | */ | ||
20 | struct dw_dma_platform_data { | ||
21 | unsigned int nr_channels; | ||
22 | }; | ||
23 | |||
24 | /** | ||
25 | * struct dw_dma_slave - Controller-specific information about a slave | ||
26 | * @slave: Generic information about the slave | ||
27 | * @ctl_lo: Platform-specific initializer for the CTL_LO register | ||
28 | * @cfg_hi: Platform-specific initializer for the CFG_HI register | ||
29 | * @cfg_lo: Platform-specific initializer for the CFG_LO register | ||
30 | */ | ||
31 | struct dw_dma_slave { | ||
32 | struct dma_slave slave; | ||
33 | u32 cfg_hi; | ||
34 | u32 cfg_lo; | ||
35 | }; | ||
36 | |||
37 | /* Platform-configurable bits in CFG_HI */ | ||
38 | #define DWC_CFGH_FCMODE (1 << 0) | ||
39 | #define DWC_CFGH_FIFO_MODE (1 << 1) | ||
40 | #define DWC_CFGH_PROTCTL(x) ((x) << 2) | ||
41 | #define DWC_CFGH_SRC_PER(x) ((x) << 7) | ||
42 | #define DWC_CFGH_DST_PER(x) ((x) << 11) | ||
43 | |||
44 | /* Platform-configurable bits in CFG_LO */ | ||
45 | #define DWC_CFGL_PRIO(x) ((x) << 5) /* priority */ | ||
46 | #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ | ||
47 | #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) | ||
48 | #define DWC_CFGL_LOCK_CH_XACT (2 << 12) | ||
49 | #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ | ||
50 | #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) | ||
51 | #define DWC_CFGL_LOCK_BUS_XACT (2 << 14) | ||
52 | #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ | ||
53 | #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ | ||
54 | #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ | ||
55 | #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ | ||
56 | |||
57 | static inline struct dw_dma_slave *to_dw_dma_slave(struct dma_slave *slave) | ||
58 | { | ||
59 | return container_of(slave, struct dw_dma_slave, slave); | ||
60 | } | ||
61 | |||
62 | #endif /* DW_DMAC_H */ | ||