aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux/dmar.h
diff options
context:
space:
mode:
authorJiang Liu <jiang.liu@linux.intel.com>2014-02-19 01:07:35 -0500
committerJoerg Roedel <joro@8bytes.org>2014-03-04 11:51:06 -0500
commit59ce0515cdaf3b7d47893d12f61e51d691863788 (patch)
tree0ba8b7a85b98fdca4fce02a5ed5a7129730f7a6c /include/linux/dmar.h
parent0e242612d9cdb46e878ed1f126c78fe68492af00 (diff)
iommu/vt-d: Update DRHD/RMRR/ATSR device scope caches when PCI hotplug happens
Current Intel DMAR/IOMMU driver assumes that all PCI devices associated with DMAR/RMRR/ATSR device scope arrays are created at boot time and won't change at runtime, so it caches pointers of associated PCI device object. That assumption may be wrong now due to: 1) introduction of PCI host bridge hotplug 2) PCI device hotplug through sysfs interfaces. Wang Yijing has tried to solve this issue by caching <bus, dev, func> tupple instead of the PCI device object pointer, but that's still unreliable because PCI bus number may change in case of hotplug. Please refer to http://lkml.org/lkml/2013/11/5/64 Message from Yingjing's mail: after remove and rescan a pci device [ 611.857095] dmar: DRHD: handling fault status reg 2 [ 611.857109] dmar: DMAR:[DMA Read] Request device [86:00.3] fault addr ffff7000 [ 611.857109] DMAR:[fault reason 02] Present bit in context entry is clear [ 611.857524] dmar: DRHD: handling fault status reg 102 [ 611.857534] dmar: DMAR:[DMA Read] Request device [86:00.3] fault addr ffff6000 [ 611.857534] DMAR:[fault reason 02] Present bit in context entry is clear [ 611.857936] dmar: DRHD: handling fault status reg 202 [ 611.857947] dmar: DMAR:[DMA Read] Request device [86:00.3] fault addr ffff5000 [ 611.857947] DMAR:[fault reason 02] Present bit in context entry is clear [ 611.858351] dmar: DRHD: handling fault status reg 302 [ 611.858362] dmar: DMAR:[DMA Read] Request device [86:00.3] fault addr ffff4000 [ 611.858362] DMAR:[fault reason 02] Present bit in context entry is clear [ 611.860819] IPv6: ADDRCONF(NETDEV_UP): eth3: link is not ready [ 611.860983] dmar: DRHD: handling fault status reg 402 [ 611.860995] dmar: INTR-REMAP: Request device [[86:00.3] fault index a4 [ 611.860995] INTR-REMAP:[fault reason 34] Present field in the IRTE entry is clear This patch introduces a new mechanism to update the DRHD/RMRR/ATSR device scope caches by hooking PCI bus notification. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
Diffstat (limited to 'include/linux/dmar.h')
-rw-r--r--include/linux/dmar.h24
1 files changed, 22 insertions, 2 deletions
diff --git a/include/linux/dmar.h b/include/linux/dmar.h
index bedebab934b4..4e196430f1b2 100644
--- a/include/linux/dmar.h
+++ b/include/linux/dmar.h
@@ -50,6 +50,15 @@ struct dmar_drhd_unit {
50 struct intel_iommu *iommu; 50 struct intel_iommu *iommu;
51}; 51};
52 52
53struct dmar_pci_notify_info {
54 struct pci_dev *dev;
55 unsigned long event;
56 int bus;
57 u16 seg;
58 u16 level;
59 struct acpi_dmar_pci_path path[];
60} __attribute__((packed));
61
53extern struct rw_semaphore dmar_global_lock; 62extern struct rw_semaphore dmar_global_lock;
54extern struct list_head dmar_drhd_units; 63extern struct list_head dmar_drhd_units;
55 64
@@ -89,12 +98,18 @@ extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
89 struct pci_dev ***devices, u16 segment); 98 struct pci_dev ***devices, u16 segment);
90extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt); 99extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt);
91extern void dmar_free_dev_scope(struct pci_dev __rcu ***devices, int *cnt); 100extern void dmar_free_dev_scope(struct pci_dev __rcu ***devices, int *cnt);
92extern void dmar_free_dev_scope(struct pci_dev ***devices, int *cnt); 101extern int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
93 102 void *start, void*end, u16 segment,
103 struct pci_dev __rcu **devices,
104 int devices_cnt);
105extern int dmar_remove_dev_scope(struct dmar_pci_notify_info *info,
106 u16 segment, struct pci_dev __rcu **devices,
107 int count);
94/* Intel IOMMU detection */ 108/* Intel IOMMU detection */
95extern int detect_intel_iommu(void); 109extern int detect_intel_iommu(void);
96extern int enable_drhd_fault_handling(void); 110extern int enable_drhd_fault_handling(void);
97#else 111#else
112struct dmar_pci_notify_info;
98static inline int detect_intel_iommu(void) 113static inline int detect_intel_iommu(void)
99{ 114{
100 return -ENODEV; 115 return -ENODEV;
@@ -161,6 +176,7 @@ extern int iommu_detected, no_iommu;
161extern int dmar_parse_rmrr_atsr_dev(void); 176extern int dmar_parse_rmrr_atsr_dev(void);
162extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header); 177extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header);
163extern int dmar_parse_one_atsr(struct acpi_dmar_header *header); 178extern int dmar_parse_one_atsr(struct acpi_dmar_header *header);
179extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info);
164extern int intel_iommu_init(void); 180extern int intel_iommu_init(void);
165#else /* !CONFIG_INTEL_IOMMU: */ 181#else /* !CONFIG_INTEL_IOMMU: */
166static inline int intel_iommu_init(void) { return -ENODEV; } 182static inline int intel_iommu_init(void) { return -ENODEV; }
@@ -176,6 +192,10 @@ static inline int dmar_parse_rmrr_atsr_dev(void)
176{ 192{
177 return 0; 193 return 0;
178} 194}
195static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
196{
197 return 0;
198}
179#endif /* CONFIG_INTEL_IOMMU */ 199#endif /* CONFIG_INTEL_IOMMU */
180 200
181#endif /* __DMAR_H__ */ 201#endif /* __DMAR_H__ */