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authorLinus Walleij <linus.walleij@stericsson.com>2010-03-26 19:50:49 -0400
committerDan Williams <dan.j.williams@intel.com>2010-03-26 19:50:49 -0400
commit0793448187643b50af89d36b08470baf45a3cab4 (patch)
treeb3313ff58d47e26a8cf707d196177effa1aadfbe /include/linux/dmaengine.h
parentc3635c78e500a52c9fcd55de381a72928d9e054d (diff)
DMAENGINE: generic channel status v2
Convert the device_is_tx_complete() operation on the DMA engine to a generic device_tx_status()operation which can return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE, DMA_TX_PAUSED. [dan.j.williams@intel.com: update for timberdale] Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Maciej Sosnowski <maciej.sosnowski@intel.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: Li Yang <leoli@freescale.com> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Magnus Damm <damm@opensource.se> Cc: Liam Girdwood <lrg@slimlogic.co.uk> Cc: Joe Perches <joe@perches.com> Cc: Roland Dreier <rdreier@cisco.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'include/linux/dmaengine.h')
-rw-r--r--include/linux/dmaengine.h38
1 files changed, 33 insertions, 5 deletions
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 0731802f876f..55b08e84ac8d 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -40,11 +40,13 @@ typedef s32 dma_cookie_t;
40 * enum dma_status - DMA transaction status 40 * enum dma_status - DMA transaction status
41 * @DMA_SUCCESS: transaction completed successfully 41 * @DMA_SUCCESS: transaction completed successfully
42 * @DMA_IN_PROGRESS: transaction not yet processed 42 * @DMA_IN_PROGRESS: transaction not yet processed
43 * @DMA_PAUSED: transaction is paused
43 * @DMA_ERROR: transaction failed 44 * @DMA_ERROR: transaction failed
44 */ 45 */
45enum dma_status { 46enum dma_status {
46 DMA_SUCCESS, 47 DMA_SUCCESS,
47 DMA_IN_PROGRESS, 48 DMA_IN_PROGRESS,
49 DMA_PAUSED,
48 DMA_ERROR, 50 DMA_ERROR,
49}; 51};
50 52
@@ -249,6 +251,21 @@ struct dma_async_tx_descriptor {
249}; 251};
250 252
251/** 253/**
254 * struct dma_tx_state - filled in to report the status of
255 * a transfer.
256 * @last: last completed DMA cookie
257 * @used: last issued DMA cookie (i.e. the one in progress)
258 * @residue: the remaining number of bytes left to transmit
259 * on the selected transfer for states DMA_IN_PROGRESS and
260 * DMA_PAUSED if this is implemented in the driver, else 0
261 */
262struct dma_tx_state {
263 dma_cookie_t last;
264 dma_cookie_t used;
265 u32 residue;
266};
267
268/**
252 * struct dma_device - info on the entity supplying DMA services 269 * struct dma_device - info on the entity supplying DMA services
253 * @chancnt: how many DMA channels are supported 270 * @chancnt: how many DMA channels are supported
254 * @privatecnt: how many DMA channels are requested by dma_request_channel 271 * @privatecnt: how many DMA channels are requested by dma_request_channel
@@ -276,7 +293,10 @@ struct dma_async_tx_descriptor {
276 * @device_prep_slave_sg: prepares a slave dma operation 293 * @device_prep_slave_sg: prepares a slave dma operation
277 * @device_control: manipulate all pending operations on a channel, returns 294 * @device_control: manipulate all pending operations on a channel, returns
278 * zero or error code 295 * zero or error code
279 * @device_is_tx_complete: poll for transaction completion 296 * @device_tx_status: poll for transaction completion, the optional
297 * txstate parameter can be supplied with a pointer to get a
298 * struct with auxilary transfer status information, otherwise the call
299 * will just return a simple status code
280 * @device_issue_pending: push pending transactions to hardware 300 * @device_issue_pending: push pending transactions to hardware
281 */ 301 */
282struct dma_device { 302struct dma_device {
@@ -329,9 +349,9 @@ struct dma_device {
329 unsigned long flags); 349 unsigned long flags);
330 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd); 350 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd);
331 351
332 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan, 352 enum dma_status (*device_tx_status)(struct dma_chan *chan,
333 dma_cookie_t cookie, dma_cookie_t *last, 353 dma_cookie_t cookie,
334 dma_cookie_t *used); 354 struct dma_tx_state *txstate);
335 void (*device_issue_pending)(struct dma_chan *chan); 355 void (*device_issue_pending)(struct dma_chan *chan);
336}; 356};
337 357
@@ -572,7 +592,15 @@ static inline void dma_async_issue_pending(struct dma_chan *chan)
572static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, 592static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
573 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) 593 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
574{ 594{
575 return chan->device->device_is_tx_complete(chan, cookie, last, used); 595 struct dma_tx_state state;
596 enum dma_status status;
597
598 status = chan->device->device_tx_status(chan, cookie, &state);
599 if (last)
600 *last = state.last;
601 if (used)
602 *used = state.used;
603 return status;
576} 604}
577 605
578#define dma_async_memcpy_complete(chan, cookie, last, used)\ 606#define dma_async_memcpy_complete(chan, cookie, last, used)\