diff options
author | Dan Williams <dan.j.williams@intel.com> | 2009-04-08 17:28:37 -0400 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2009-04-08 17:28:37 -0400 |
commit | 099f53cb50e45ef617a9f1d63ceec799e489418b (patch) | |
tree | fd57f259f58bcf615fe2b17734ed0cbec612782d /include/linux/dmaengine.h | |
parent | fd74ea65883c7e6903e9b652795f72b723a2be69 (diff) |
async_tx: rename zero_sum to val
'zero_sum' does not properly describe the operation of generating parity
and checking that it validates against an existing buffer. Change the
name of the operation to 'val' (for 'validate'). This is in
anticipation of the p+q case where it is a requirement to identify the
target parity buffers separately from the source buffers, because the
target parity buffers will not have corresponding pq coefficients.
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'include/linux/dmaengine.h')
-rw-r--r-- | include/linux/dmaengine.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 2e2aa3df170c..6768727d00d7 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h | |||
@@ -55,8 +55,8 @@ enum dma_transaction_type { | |||
55 | DMA_PQ_XOR, | 55 | DMA_PQ_XOR, |
56 | DMA_DUAL_XOR, | 56 | DMA_DUAL_XOR, |
57 | DMA_PQ_UPDATE, | 57 | DMA_PQ_UPDATE, |
58 | DMA_ZERO_SUM, | 58 | DMA_XOR_VAL, |
59 | DMA_PQ_ZERO_SUM, | 59 | DMA_PQ_VAL, |
60 | DMA_MEMSET, | 60 | DMA_MEMSET, |
61 | DMA_MEMCPY_CRC32C, | 61 | DMA_MEMCPY_CRC32C, |
62 | DMA_INTERRUPT, | 62 | DMA_INTERRUPT, |
@@ -214,7 +214,7 @@ struct dma_async_tx_descriptor { | |||
214 | * @device_free_chan_resources: release DMA channel's resources | 214 | * @device_free_chan_resources: release DMA channel's resources |
215 | * @device_prep_dma_memcpy: prepares a memcpy operation | 215 | * @device_prep_dma_memcpy: prepares a memcpy operation |
216 | * @device_prep_dma_xor: prepares a xor operation | 216 | * @device_prep_dma_xor: prepares a xor operation |
217 | * @device_prep_dma_zero_sum: prepares a zero_sum operation | 217 | * @device_prep_dma_xor_val: prepares a xor validation operation |
218 | * @device_prep_dma_memset: prepares a memset operation | 218 | * @device_prep_dma_memset: prepares a memset operation |
219 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation | 219 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation |
220 | * @device_prep_slave_sg: prepares a slave dma operation | 220 | * @device_prep_slave_sg: prepares a slave dma operation |
@@ -243,7 +243,7 @@ struct dma_device { | |||
243 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( | 243 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
244 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | 244 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
245 | unsigned int src_cnt, size_t len, unsigned long flags); | 245 | unsigned int src_cnt, size_t len, unsigned long flags); |
246 | struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( | 246 | struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( |
247 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, | 247 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
248 | size_t len, u32 *result, unsigned long flags); | 248 | size_t len, u32 *result, unsigned long flags); |
249 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( | 249 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |