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authorLinus Walleij <linus.walleij@stericsson.com>2010-03-26 19:44:01 -0400
committerDan Williams <dan.j.williams@intel.com>2010-03-26 19:44:01 -0400
commitc3635c78e500a52c9fcd55de381a72928d9e054d (patch)
tree87403f402227cd8b5572550e70facf81c9eaa0d9 /include/linux/dmaengine.h
parent0f65169b1bf44220308e1ce1f6666ad03ddc27af (diff)
DMAENGINE: generic slave control v2
Convert the device_terminate_all() operation on the DMA engine to a generic device_control() operation which can now optionally support also pausing and resuming DMA on a certain channel. Implemented for the COH 901 318 DMAC as an example. [dan.j.williams@intel.com: update for timberdale] Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Maciej Sosnowski <maciej.sosnowski@intel.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: Li Yang <leoli@freescale.com> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Magnus Damm <damm@opensource.se> Cc: Liam Girdwood <lrg@slimlogic.co.uk> Cc: Joe Perches <joe@perches.com> Cc: Roland Dreier <rdreier@cisco.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'include/linux/dmaengine.h')
-rw-r--r--include/linux/dmaengine.h18
1 files changed, 16 insertions, 2 deletions
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 20ea12c86fd0..0731802f876f 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -107,6 +107,19 @@ enum dma_ctrl_flags {
107}; 107};
108 108
109/** 109/**
110 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
111 * on a running channel.
112 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
113 * @DMA_PAUSE: pause ongoing transfers
114 * @DMA_RESUME: resume paused transfer
115 */
116enum dma_ctrl_cmd {
117 DMA_TERMINATE_ALL,
118 DMA_PAUSE,
119 DMA_RESUME,
120};
121
122/**
110 * enum sum_check_bits - bit position of pq_check_flags 123 * enum sum_check_bits - bit position of pq_check_flags
111 */ 124 */
112enum sum_check_bits { 125enum sum_check_bits {
@@ -261,7 +274,8 @@ struct dma_async_tx_descriptor {
261 * @device_prep_dma_memset: prepares a memset operation 274 * @device_prep_dma_memset: prepares a memset operation
262 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation 275 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
263 * @device_prep_slave_sg: prepares a slave dma operation 276 * @device_prep_slave_sg: prepares a slave dma operation
264 * @device_terminate_all: terminate all pending operations 277 * @device_control: manipulate all pending operations on a channel, returns
278 * zero or error code
265 * @device_is_tx_complete: poll for transaction completion 279 * @device_is_tx_complete: poll for transaction completion
266 * @device_issue_pending: push pending transactions to hardware 280 * @device_issue_pending: push pending transactions to hardware
267 */ 281 */
@@ -313,7 +327,7 @@ struct dma_device {
313 struct dma_chan *chan, struct scatterlist *sgl, 327 struct dma_chan *chan, struct scatterlist *sgl,
314 unsigned int sg_len, enum dma_data_direction direction, 328 unsigned int sg_len, enum dma_data_direction direction,
315 unsigned long flags); 329 unsigned long flags);
316 void (*device_terminate_all)(struct dma_chan *chan); 330 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd);
317 331
318 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan, 332 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
319 dma_cookie_t cookie, dma_cookie_t *last, 333 dma_cookie_t cookie, dma_cookie_t *last,