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authorMike Turquette <mturquette@linaro.org>2013-04-11 14:31:36 -0400
committerMike Turquette <mturquette@linaro.org>2013-04-12 14:22:35 -0400
commitd3a1c7be8361e2fbb6affbdb19de47ca48d6c402 (patch)
tree2371cf7b528092b13bd8a178f77a9c5aa0a947ad /include/linux/clk-provider.h
parent9abd5f0555df6cd36130feb742f1def6d99c60fe (diff)
clk: composite: rename 'div' references to 'rate'
Rename all div_hw and div_ops related variables and functions to use rate_hw, rate_ops, etc. This is to make the rate-change portion of the composite clk implementation more generic. A patch following this one will allow for fixed-rate clocks to reuse this infrastructure. Signed-off-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Emilio López <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'include/linux/clk-provider.h')
-rw-r--r--include/linux/clk-provider.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index e7b7cbc53815..11860985fecb 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -354,11 +354,11 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
354 * struct clk_composite - aggregate clock of mux, divider and gate clocks 354 * struct clk_composite - aggregate clock of mux, divider and gate clocks
355 * 355 *
356 * @hw: handle between common and hardware-specific interfaces 356 * @hw: handle between common and hardware-specific interfaces
357 * @mux_hw: handle between composite and hardware-specifix mux clock 357 * @mux_hw: handle between composite and hardware-specific mux clock
358 * @div_hw: handle between composite and hardware-specifix divider clock 358 * @rate_hw: handle between composite and hardware-specific rate clock
359 * @gate_hw: handle between composite and hardware-specifix gate clock 359 * @gate_hw: handle between composite and hardware-specific gate clock
360 * @mux_ops: clock ops for mux 360 * @mux_ops: clock ops for mux
361 * @div_ops: clock ops for divider 361 * @rate_ops: clock ops for rate
362 * @gate_ops: clock ops for gate 362 * @gate_ops: clock ops for gate
363 */ 363 */
364struct clk_composite { 364struct clk_composite {
@@ -366,18 +366,18 @@ struct clk_composite {
366 struct clk_ops ops; 366 struct clk_ops ops;
367 367
368 struct clk_hw *mux_hw; 368 struct clk_hw *mux_hw;
369 struct clk_hw *div_hw; 369 struct clk_hw *rate_hw;
370 struct clk_hw *gate_hw; 370 struct clk_hw *gate_hw;
371 371
372 const struct clk_ops *mux_ops; 372 const struct clk_ops *mux_ops;
373 const struct clk_ops *div_ops; 373 const struct clk_ops *rate_ops;
374 const struct clk_ops *gate_ops; 374 const struct clk_ops *gate_ops;
375}; 375};
376 376
377struct clk *clk_register_composite(struct device *dev, const char *name, 377struct clk *clk_register_composite(struct device *dev, const char *name,
378 const char **parent_names, int num_parents, 378 const char **parent_names, int num_parents,
379 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 379 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
380 struct clk_hw *div_hw, const struct clk_ops *div_ops, 380 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
381 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 381 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
382 unsigned long flags); 382 unsigned long flags);
383 383