clk: mux: add CLK_MUX_HIWORD_MASK

In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the
paradigm of reading-changing-writing the register contents.
Instead they use a hiword mask to indicate the changed bits.

When b01 should be set as switching mux, it also needs to indicate
the change by setting hiword mask (b11 << 16).

The patch adds mux flag for this usage.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 5 insertions, 0 deletions

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 265f384f1e01..37ad97961e5a 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -299,6 +299,10 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
  * Flags:
  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
+ * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
+ *   register, and mask of mux bits are in higher 16-bit of this register.
+ *   While setting the mux bits, higher 16-bit should also be updated to
+ *   indicate changing mux bits.
  */
 struct clk_mux {
         struct clk_hw   hw;
@@ -312,6 +316,7 @@ struct clk_mux {
 
 #define CLK_MUX_INDEX_ONE               BIT(0)
 #define CLK_MUX_INDEX_BIT               BIT(1)
+#define CLK_MUX_HIWORD_MASK             BIT(2)
 
 extern const struct clk_ops clk_mux_ops;