clk: Add set_rate_and_parent() op

Some of Qualcomm's clocks can change their parent and rate at the
same time with a single register write. Add support for this
hardware to the common clock framework by adding a new
set_rate_and_parent() op. When the clock framework determines
that both the parent and the rate are going to change during
clk_set_rate() it will call the .set_rate_and_parent() op if
available and fall back to calling .set_parent() followed by
.set_rate() otherwise.

Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 15 insertions, 0 deletions

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5429f5db5037..999b28ba38f7 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -116,6 +116,18 @@ struct clk_hw;
  *              set then clock accuracy will be initialized to parent accuracy
  *              or 0 (perfect clock) if clock has no parent.
  *
+ * @set_rate_and_parent: Change the rate and the parent of this clock. The
+ *              requested rate is specified by the second argument, which
+ *              should typically be the return of .round_rate call.  The
+ *              third argument gives the parent rate which is likely helpful
+ *              for most .set_rate_and_parent implementation. The fourth
+ *              argument gives the parent index. This callback is optional (and
+ *              unnecessary) for clocks with 0 or 1 parents as well as
+ *              for clocks that can tolerate switching the rate and the parent
+ *              separately via calls to .set_parent and .set_rate.
+ *              Returns 0 on success, -EERROR otherwise.
+ *
+ *
  * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
  * implementations to split any work between atomic (enable) and sleepable
  * (prepare) contexts.  If enabling a clock requires code that might sleep,
@@ -147,6 +159,9 @@ struct clk_ops {
         u8              (*get_parent)(struct clk_hw *hw);
         int             (*set_rate)(struct clk_hw *hw, unsigned long,
                                     unsigned long);
+        int             (*set_rate_and_parent)(struct clk_hw *hw,
+                                    unsigned long rate,
+                                    unsigned long parent_rate, u8 index);
         unsigned long   (*recalc_accuracy)(struct clk_hw *hw,
                                            unsigned long parent_accuracy);
         void            (*init)(struct clk_hw *hw);