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authorFranky Lin <frankyl@broadcom.com>2013-04-11 07:28:51 -0400
committerJohn W. Linville <linville@tuxdriver.com>2013-04-12 14:27:54 -0400
commit1640f28f6b839637d9b82a3c4a19120601e59c66 (patch)
treeaa993155ba1352b8c26b7aa3a9fe3651925dbf37 /include/linux/bcma
parent83cf17aa80820248178deb7ca263123cced179dc (diff)
brcmfmac: add support for dongle ARM CR4 core
Newer WiFi chip use ARM CR4 core to achieve higher performance. Add necessary code for host driver in order to support CR4 core. Reviewed-by: Arend van Spriel <arend@broadcom.com> Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include/linux/bcma')
-rw-r--r--include/linux/bcma/bcma.h1
-rw-r--r--include/linux/bcma/bcma_regs.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
index 0ab6712fd76b..f14a98a79c9d 100644
--- a/include/linux/bcma/bcma.h
+++ b/include/linux/bcma/bcma.h
@@ -134,6 +134,7 @@ struct bcma_host_ops {
134#define BCMA_CORE_I2S 0x834 134#define BCMA_CORE_I2S 0x834
135#define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */ 135#define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
136#define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */ 136#define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
137#define BCMA_CORE_ARM_CR4 0x83e
137#define BCMA_CORE_DEFAULT 0xFFF 138#define BCMA_CORE_DEFAULT 0xFFF
138 139
139#define BCMA_MAX_NR_CORES 16 140#define BCMA_MAX_NR_CORES 16
diff --git a/include/linux/bcma/bcma_regs.h b/include/linux/bcma/bcma_regs.h
index 7e8104bb7a7e..917dcd7965e7 100644
--- a/include/linux/bcma/bcma_regs.h
+++ b/include/linux/bcma/bcma_regs.h
@@ -37,6 +37,7 @@
37#define BCMA_IOST_BIST_DONE 0x8000 37#define BCMA_IOST_BIST_DONE 0x8000
38#define BCMA_RESET_CTL 0x0800 38#define BCMA_RESET_CTL 0x0800
39#define BCMA_RESET_CTL_RESET 0x0001 39#define BCMA_RESET_CTL_RESET 0x0001
40#define BCMA_RESET_ST 0x0804
40 41
41/* BCMA PCI config space registers. */ 42/* BCMA PCI config space registers. */
42#define BCMA_PCI_PMCSR 0x44 43#define BCMA_PCI_PMCSR 0x44