diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-08-03 17:31:24 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-08-03 17:31:24 -0400 |
| commit | be82ae0238b0453afcf4a76f0512b7dde34ba500 (patch) | |
| tree | aaa3f5f11fd51fd73365ee1a2164aad9a03de060 /include/linux/amba/serial.h | |
| parent | 4b4fd27c0b5ec638a1f06ced9226fd95229dbbf0 (diff) | |
| parent | 7b70c4275f28702b76b273c8534c38f8313812e9 (diff) | |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (291 commits)
ARM: AMBA: Add pclk support to AMBA bus infrastructure
ARM: 6278/2: fix regression in RealView after the introduction of pclk
ARM: 6277/1: mach-shmobile: Allow users to select HZ, default to 128
ARM: 6276/1: mach-shmobile: remove duplicate NR_IRQS_LEGACY
ARM: 6246/1: mmci: support larger MMCIDATALENGTH register
ARM: 6245/1: mmci: enable hardware flow control on Ux500 variants
ARM: 6244/1: mmci: add variant data and default MCICLOCK support
ARM: 6243/1: mmci: pass power_mode to the translate_vdd callback
ARM: 6274/1: add global control registers definition header file for nuc900
mx2_camera: fix type of dma buffer virtual address pointer
mx2_camera: Add soc_camera support for i.MX25/i.MX27
arm/imx/gpio: add spinlock protection
ARM: Add support for the LPC32XX arch
ARM: LPC32XX: Arch config menu supoport and makefiles
ARM: LPC32XX: Phytec 3250 platform support
ARM: LPC32XX: Misc support functions
ARM: LPC32XX: Serial support code
ARM: LPC32XX: System suspend support
ARM: LPC32XX: GPIO, timer, and IRQ drivers
ARM: LPC32XX: Clock driver
...
Diffstat (limited to 'include/linux/amba/serial.h')
| -rw-r--r-- | include/linux/amba/serial.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h index 5a5a7fd62490..e1b634b635f2 100644 --- a/include/linux/amba/serial.h +++ b/include/linux/amba/serial.h | |||
| @@ -38,10 +38,12 @@ | |||
| 38 | #define UART01x_FR 0x18 /* Flag register (Read only). */ | 38 | #define UART01x_FR 0x18 /* Flag register (Read only). */ |
| 39 | #define UART010_IIR 0x1C /* Interrupt indentification register (Read). */ | 39 | #define UART010_IIR 0x1C /* Interrupt indentification register (Read). */ |
| 40 | #define UART010_ICR 0x1C /* Interrupt clear register (Write). */ | 40 | #define UART010_ICR 0x1C /* Interrupt clear register (Write). */ |
| 41 | #define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */ | ||
| 41 | #define UART01x_ILPR 0x20 /* IrDA low power counter register. */ | 42 | #define UART01x_ILPR 0x20 /* IrDA low power counter register. */ |
| 42 | #define UART011_IBRD 0x24 /* Integer baud rate divisor register. */ | 43 | #define UART011_IBRD 0x24 /* Integer baud rate divisor register. */ |
| 43 | #define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */ | 44 | #define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */ |
| 44 | #define UART011_LCRH 0x2c /* Line control register. */ | 45 | #define UART011_LCRH 0x2c /* Line control register. */ |
| 46 | #define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */ | ||
| 45 | #define UART011_CR 0x30 /* Control register. */ | 47 | #define UART011_CR 0x30 /* Control register. */ |
| 46 | #define UART011_IFLS 0x34 /* Interrupt fifo level select. */ | 48 | #define UART011_IFLS 0x34 /* Interrupt fifo level select. */ |
| 47 | #define UART011_IMSC 0x38 /* Interrupt mask. */ | 49 | #define UART011_IMSC 0x38 /* Interrupt mask. */ |
| @@ -84,6 +86,7 @@ | |||
| 84 | #define UART010_CR_TIE 0x0020 | 86 | #define UART010_CR_TIE 0x0020 |
| 85 | #define UART010_CR_RIE 0x0010 | 87 | #define UART010_CR_RIE 0x0010 |
| 86 | #define UART010_CR_MSIE 0x0008 | 88 | #define UART010_CR_MSIE 0x0008 |
| 89 | #define ST_UART011_CR_OVSFACT 0x0008 /* Oversampling factor */ | ||
| 87 | #define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */ | 90 | #define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */ |
| 88 | #define UART01x_CR_SIREN 0x0002 /* SIR enable */ | 91 | #define UART01x_CR_SIREN 0x0002 /* SIR enable */ |
| 89 | #define UART01x_CR_UARTEN 0x0001 /* UART enable */ | 92 | #define UART01x_CR_UARTEN 0x0001 /* UART enable */ |