arm/arm64: KVM: vgic: switch to dynamic allocation

So far, all the VGIC data structures are statically defined by the
*maximum* number of vcpus and interrupts it supports. It means that
we always have to oversize it to cater for the worse case.

Start by changing the data structures to be dynamically sizeable,
and allocate them at runtime.

The sizes are still very static though.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

1 files changed, 58 insertions, 18 deletions

diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index f074539c6ac5..fd1b8f252da1 100644
--- a/include/kvm/arm_vgic.h
+++ b/include/kvm/arm_vgic.h
@@ -54,19 +54,33 @@
  * - a bunch of shared interrupts (SPI)
  */
 struct vgic_bitmap {
-        union {
-                u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
-                DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
-        } percpu[VGIC_MAX_CPUS];
-        union {
-                u32 reg[VGIC_NR_SHARED_IRQS / 32];
-                DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
-        } shared;
+        /*
+         * - One UL per VCPU for private interrupts (assumes UL is at
+         *   least 32 bits)
+         * - As many UL as necessary for shared interrupts.
+         *
+         * The private interrupts are accessed via the "private"
+         * field, one UL per vcpu (the state for vcpu n is in
+         * private[n]). The shared interrupts are accessed via the
+         * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
+         */
+        unsigned long *private;
+        unsigned long *shared;
 };
 
 struct vgic_bytemap {
-        u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
-        u32 shared[VGIC_NR_SHARED_IRQS  / 4];
+        /*
+         * - 8 u32 per VCPU for private interrupts
+         * - As many u32 as necessary for shared interrupts.
+         *
+         * The private interrupts are accessed via the "private"
+         * field, (the state for vcpu n is in private[n*8] to
+         * private[n*8 + 7]). The shared interrupts are accessed via
+         * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
+         * shared[(n-32)/4] word).
+         */
+        u32 *private;
+        u32 *shared;
 };
 
 struct kvm_vcpu;
@@ -127,6 +141,9 @@ struct vgic_dist {
         bool                    in_kernel;
         bool                    ready;
 
+        int                     nr_cpus;
+        int                     nr_irqs;
+
         /* Virtual control interface mapping */
         void __iomem            *vctrl_base;
 
@@ -166,15 +183,36 @@ struct vgic_dist {
         /* Level/edge triggered */
         struct vgic_bitmap      irq_cfg;
 
-        /* Source CPU per SGI and target CPU */
-        u8                      irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
+        /*
+         * Source CPU per SGI and target CPU:
+         *
+         * Each byte represent a SGI observable on a VCPU, each bit of
+         * this byte indicating if the corresponding VCPU has
+         * generated this interrupt. This is a GICv2 feature only.
+         *
+         * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
+         * the SGIs observable on VCPUn.
+         */
+        u8                      *irq_sgi_sources;
 
-        /* Target CPU for each IRQ */
-        u8                      irq_spi_cpu[VGIC_NR_SHARED_IRQS];
-        struct vgic_bitmap      irq_spi_target[VGIC_MAX_CPUS];
+        /*
+         * Target CPU for each SPI:
+         *
+         * Array of available SPI, each byte indicating the target
+         * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
+         */
+        u8                      *irq_spi_cpu;
+
+        /*
+         * Reverse lookup of irq_spi_cpu for faster compute pending:
+         *
+         * Array of bitmaps, one per VCPU, describing if IRQn is
+         * routed to a particular VCPU.
+         */
+        struct vgic_bitmap      *irq_spi_target;
 
         /* Bitmap indicating which CPU has something pending */
-        unsigned long           irq_pending_on_cpu;
+        unsigned long           *irq_pending_on_cpu;
 #endif
 };
 
@@ -204,11 +242,11 @@ struct vgic_v3_cpu_if {
 struct vgic_cpu {
 #ifdef CONFIG_KVM_ARM_VGIC
         /* per IRQ to LR mapping */
-        u8              vgic_irq_lr_map[VGIC_NR_IRQS];
+        u8              *vgic_irq_lr_map;
 
         /* Pending interrupts on this VCPU */
         DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
-        DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
+        unsigned long   *pending_shared;
 
         /* Bitmap of used/free list registers */
         DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
@@ -239,7 +277,9 @@ int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
 int kvm_vgic_hyp_init(void);
 int kvm_vgic_init(struct kvm *kvm);
 int kvm_vgic_create(struct kvm *kvm);
+void kvm_vgic_destroy(struct kvm *kvm);
 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
+void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,