clk: samsung: exynos4: Add divider clock id for memory bus frequency

This patch adds the divider clock id for Exynos4 memory bus frequency.
The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling)
feature of the exynos memory bus.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

1 files changed, 6 insertions, 1 deletions

diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 34fe28c622d0..c4b1676ea674 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -262,8 +262,13 @@
 #define CLK_DIV_MCUISP1         453 /* Exynos4x12 only */
 #define CLK_DIV_ACLK200         454 /* Exynos4x12 only */
 #define CLK_DIV_ACLK400_MCUISP  455 /* Exynos4x12 only */
+#define CLK_DIV_ACP             456
+#define CLK_DIV_DMC             457
+#define CLK_DIV_C2C             458 /* Exynos4x12 only */
+#define CLK_DIV_GDL             459
+#define CLK_DIV_GDR             460
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS             456
+#define CLK_NR_CLKS             461
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */