Merge tag 'v3.17-rc3' into next

Sync with mainline to bring in Chrome EC changes.
author: Dmitry Torokhov <dmitry.torokhov@gmail.com> 2014-09-03 19:01:36 -0400
committer: Dmitry Torokhov <dmitry.torokhov@gmail.com> 2014-09-03 19:01:36 -0400
commit: 516d5f8b04ce2bcd24f03323fc743ae25b81373d (patch)
tree: ff37e84692dbef5063bbf22672eb8bfad0f25dd8 /include/dt-bindings
parent: 6ba694560caeb3531dbedd5b3a37af037ef2a833 (diff)
parent: 69e273c0b0a3c337a521d083374c918dc52c666f (diff)
34 files changed, 2688 insertions, 9 deletions
diff --git a/include/dt-bindings/clock/clps711x-clock.h b/include/dt-bindings/clock/clps711x-clock.h
new file mode 100644
index 000000000000..0c4c80b63242
--- /dev/null
+++ b/include/dt-bindings/clock/clps711x-clock.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __DT_BINDINGS_CLOCK_CLPS711X_H
+#define __DT_BINDINGS_CLOCK_CLPS711X_H
+#define CLPS711X_CLK_DUMMY      0
+#define CLPS711X_CLK_CPU        1
+#define CLPS711X_CLK_BUS        2
+#define CLPS711X_CLK_PLL        3
+#define CLPS711X_CLK_TIMERREF   4
+#define CLPS711X_CLK_TIMER1     5
+#define CLPS711X_CLK_TIMER2     6
+#define CLPS711X_CLK_PWM        7
+#define CLPS711X_CLK_SPIREF     8
+#define CLPS711X_CLK_SPI        9
+#define CLPS711X_CLK_UART       10
+#define CLPS711X_CLK_TICK       11
+#define CLPS711X_CLK_MAX        12
+#endif
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 1106ca540a96..459bd2bd411f 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
- * Author: Andrzej Haja <a.hajda@samsung.com>
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -34,6 +34,11 @@
 #define CLK_MOUT_CORE           19
 #define CLK_MOUT_APLL           20
 #define CLK_SCLK_HDMIPHY        22
+#define CLK_OUT_DMC             23
+#define CLK_OUT_TOP             24
+#define CLK_OUT_LEFTBUS         25
+#define CLK_OUT_RIGHTBUS        26
+#define CLK_OUT_CPU             27
 /* gate for special clocks (sclk) */
 #define CLK_SCLK_FIMC0          128
@@ -230,6 +235,24 @@
 #define CLK_MOUT_G3D            394
 #define CLK_ACLK400_MCUISP      395 /* Exynos4x12 only */
+/* gate clocks - ppmu */
+#define CLK_PPMULEFT            400
+#define CLK_PPMURIGHT           401
+#define CLK_PPMUCAMIF           402
+#define CLK_PPMUTV              403
+#define CLK_PPMUMFC_L           404
+#define CLK_PPMUMFC_R           405
+#define CLK_PPMUG3D             406
+#define CLK_PPMUIMAGE           407
+#define CLK_PPMULCD0            408
+#define CLK_PPMULCD1            409 /* Exynos4210 only */
+#define CLK_PPMUFILE            410
+#define CLK_PPMUGPS             411
+#define CLK_PPMUDMC0            412
+#define CLK_PPMUDMC1            413
+#define CLK_PPMUCPU             414
+#define CLK_PPMUACP             415
 /* div clocks */
 #define CLK_DIV_ISP0            450 /* Exynos4x12 only */
 #define CLK_DIV_ISP1            451 /* Exynos4x12 only */
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index be6e97c54f54..4273891dc78e 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
- * Author: Andrzej Haja <a.hajda@samsung.com>
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 21d51ae1d242..8dc0913f1775 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
- * Author: Andrzej Haja <a.hajda@samsung.com>
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/include/dt-bindings/clock/exynos5440.h b/include/dt-bindings/clock/exynos5440.h
index 70cd85077fa9..c66fc405a79a 100644
--- a/include/dt-bindings/clock/exynos5440.h
+++ b/include/dt-bindings/clock/exynos5440.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
- * Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/include/dt-bindings/clock/imx1-clock.h b/include/dt-bindings/clock/imx1-clock.h
new file mode 100644
index 000000000000..607bf01a31dd
--- /dev/null
+++ b/include/dt-bindings/clock/imx1-clock.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __DT_BINDINGS_CLOCK_IMX1_H
+#define __DT_BINDINGS_CLOCK_IMX1_H
+#define IMX1_CLK_DUMMY          0
+#define IMX1_CLK_CLK32          1
+#define IMX1_CLK_CLK16M_EXT     2
+#define IMX1_CLK_CLK16M         3
+#define IMX1_CLK_CLK32_PREMULT  4
+#define IMX1_CLK_PREM           5
+#define IMX1_CLK_MPLL           6
+#define IMX1_CLK_MPLL_GATE      7
+#define IMX1_CLK_SPLL           8
+#define IMX1_CLK_SPLL_GATE      9
+#define IMX1_CLK_MCU            10
+#define IMX1_CLK_FCLK           11
+#define IMX1_CLK_HCLK           12
+#define IMX1_CLK_CLK48M         13
+#define IMX1_CLK_PER1           14
+#define IMX1_CLK_PER2           15
+#define IMX1_CLK_PER3           16
+#define IMX1_CLK_CLKO           17
+#define IMX1_CLK_UART3_GATE     18
+#define IMX1_CLK_SSI2_GATE      19
+#define IMX1_CLK_BROM_GATE      20
+#define IMX1_CLK_DMA_GATE       21
+#define IMX1_CLK_CSI_GATE       22
+#define IMX1_CLK_MMA_GATE       23
+#define IMX1_CLK_USBD_GATE      24
+#define IMX1_CLK_MAX            25
+#endif
diff --git a/include/dt-bindings/clock/imx21-clock.h b/include/dt-bindings/clock/imx21-clock.h
new file mode 100644
index 000000000000..b13596cf51b2
--- /dev/null
+++ b/include/dt-bindings/clock/imx21-clock.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __DT_BINDINGS_CLOCK_IMX21_H
+#define __DT_BINDINGS_CLOCK_IMX21_H
+#define IMX21_CLK_DUMMY                 0
+#define IMX21_CLK_CKIL                  1
+#define IMX21_CLK_CKIH                  2
+#define IMX21_CLK_FPM                   3
+#define IMX21_CLK_CKIH_DIV1P5           4
+#define IMX21_CLK_MPLL_GATE             5
+#define IMX21_CLK_SPLL_GATE             6
+#define IMX21_CLK_FPM_GATE              7
+#define IMX21_CLK_CKIH_GATE             8
+#define IMX21_CLK_MPLL_OSC_SEL          9
+#define IMX21_CLK_IPG                   10
+#define IMX21_CLK_HCLK                  11
+#define IMX21_CLK_MPLL_SEL              12
+#define IMX21_CLK_SPLL_SEL              13
+#define IMX21_CLK_SSI1_SEL              14
+#define IMX21_CLK_SSI2_SEL              15
+#define IMX21_CLK_USB_DIV               16
+#define IMX21_CLK_FCLK                  17
+#define IMX21_CLK_MPLL                  18
+#define IMX21_CLK_SPLL                  19
+#define IMX21_CLK_NFC_DIV               20
+#define IMX21_CLK_SSI1_DIV              21
+#define IMX21_CLK_SSI2_DIV              22
+#define IMX21_CLK_PER1                  23
+#define IMX21_CLK_PER2                  24
+#define IMX21_CLK_PER3                  25
+#define IMX21_CLK_PER4                  26
+#define IMX21_CLK_UART1_IPG_GATE        27
+#define IMX21_CLK_UART2_IPG_GATE        28
+#define IMX21_CLK_UART3_IPG_GATE        29
+#define IMX21_CLK_UART4_IPG_GATE        30
+#define IMX21_CLK_CSPI1_IPG_GATE        31
+#define IMX21_CLK_CSPI2_IPG_GATE        32
+#define IMX21_CLK_SSI1_GATE             33
+#define IMX21_CLK_SSI2_GATE             34
+#define IMX21_CLK_SDHC1_IPG_GATE        35
+#define IMX21_CLK_SDHC2_IPG_GATE        36
+#define IMX21_CLK_GPIO_GATE             37
+#define IMX21_CLK_I2C_GATE              38
+#define IMX21_CLK_DMA_GATE              39
+#define IMX21_CLK_USB_GATE              40
+#define IMX21_CLK_EMMA_GATE             41
+#define IMX21_CLK_SSI2_BAUD_GATE        42
+#define IMX21_CLK_SSI1_BAUD_GATE        43
+#define IMX21_CLK_LCDC_IPG_GATE         44
+#define IMX21_CLK_NFC_GATE              45
+#define IMX21_CLK_LCDC_HCLK_GATE        46
+#define IMX21_CLK_PER4_GATE             47
+#define IMX21_CLK_BMI_GATE              48
+#define IMX21_CLK_USB_HCLK_GATE         49
+#define IMX21_CLK_SLCDC_GATE            50
+#define IMX21_CLK_SLCDC_HCLK_GATE       51
+#define IMX21_CLK_EMMA_HCLK_GATE        52
+#define IMX21_CLK_BROM_GATE             53
+#define IMX21_CLK_DMA_HCLK_GATE         54
+#define IMX21_CLK_CSI_HCLK_GATE         55
+#define IMX21_CLK_CSPI3_IPG_GATE        56
+#define IMX21_CLK_WDOG_GATE             57
+#define IMX21_CLK_GPT1_IPG_GATE         58
+#define IMX21_CLK_GPT2_IPG_GATE         59
+#define IMX21_CLK_GPT3_IPG_GATE         60
+#define IMX21_CLK_PWM_IPG_GATE          61
+#define IMX21_CLK_RTC_GATE              62
+#define IMX21_CLK_KPP_GATE              63
+#define IMX21_CLK_OWIRE_GATE            64
+#define IMX21_CLK_MAX                   65
+#endif
diff --git a/include/dt-bindings/clock/imx27-clock.h b/include/dt-bindings/clock/imx27-clock.h
new file mode 100644
index 000000000000..148b053e54ec
--- /dev/null
+++ b/include/dt-bindings/clock/imx27-clock.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __DT_BINDINGS_CLOCK_IMX27_H
+#define __DT_BINDINGS_CLOCK_IMX27_H
+#define IMX27_CLK_DUMMY                 0
+#define IMX27_CLK_CKIH                  1
+#define IMX27_CLK_CKIL                  2
+#define IMX27_CLK_MPLL                  3
+#define IMX27_CLK_SPLL                  4
+#define IMX27_CLK_MPLL_MAIN2            5
+#define IMX27_CLK_AHB                   6
+#define IMX27_CLK_IPG                   7
+#define IMX27_CLK_NFC_DIV               8
+#define IMX27_CLK_PER1_DIV              9
+#define IMX27_CLK_PER2_DIV              10
+#define IMX27_CLK_PER3_DIV              11
+#define IMX27_CLK_PER4_DIV              12
+#define IMX27_CLK_VPU_SEL               13
+#define IMX27_CLK_VPU_DIV               14
+#define IMX27_CLK_USB_DIV               15
+#define IMX27_CLK_CPU_SEL               16
+#define IMX27_CLK_CLKO_SEL              17
+#define IMX27_CLK_CPU_DIV               18
+#define IMX27_CLK_CLKO_DIV              19
+#define IMX27_CLK_SSI1_SEL              20
+#define IMX27_CLK_SSI2_SEL              21
+#define IMX27_CLK_SSI1_DIV              22
+#define IMX27_CLK_SSI2_DIV              23
+#define IMX27_CLK_CLKO_EN               24
+#define IMX27_CLK_SSI2_IPG_GATE         25
+#define IMX27_CLK_SSI1_IPG_GATE         26
+#define IMX27_CLK_SLCDC_IPG_GATE        27
+#define IMX27_CLK_SDHC3_IPG_GATE        28
+#define IMX27_CLK_SDHC2_IPG_GATE        29
+#define IMX27_CLK_SDHC1_IPG_GATE        30
+#define IMX27_CLK_SCC_IPG_GATE          31
+#define IMX27_CLK_SAHARA_IPG_GATE       32
+#define IMX27_CLK_RTC_IPG_GATE          33
+#define IMX27_CLK_PWM_IPG_GATE          34
+#define IMX27_CLK_OWIRE_IPG_GATE        35
+#define IMX27_CLK_LCDC_IPG_GATE         36
+#define IMX27_CLK_KPP_IPG_GATE          37
+#define IMX27_CLK_IIM_IPG_GATE          38
+#define IMX27_CLK_I2C2_IPG_GATE         39
+#define IMX27_CLK_I2C1_IPG_GATE         40
+#define IMX27_CLK_GPT6_IPG_GATE         41
+#define IMX27_CLK_GPT5_IPG_GATE         42
+#define IMX27_CLK_GPT4_IPG_GATE         43
+#define IMX27_CLK_GPT3_IPG_GATE         44
+#define IMX27_CLK_GPT2_IPG_GATE         45
+#define IMX27_CLK_GPT1_IPG_GATE         46
+#define IMX27_CLK_GPIO_IPG_GATE         47
+#define IMX27_CLK_FEC_IPG_GATE          48
+#define IMX27_CLK_EMMA_IPG_GATE         49
+#define IMX27_CLK_DMA_IPG_GATE          50
+#define IMX27_CLK_CSPI3_IPG_GATE        51
+#define IMX27_CLK_CSPI2_IPG_GATE        52
+#define IMX27_CLK_CSPI1_IPG_GATE        53
+#define IMX27_CLK_NFC_BAUD_GATE         54
+#define IMX27_CLK_SSI2_BAUD_GATE        55
+#define IMX27_CLK_SSI1_BAUD_GATE        56
+#define IMX27_CLK_VPU_BAUD_GATE         57
+#define IMX27_CLK_PER4_GATE             58
+#define IMX27_CLK_PER3_GATE             59
+#define IMX27_CLK_PER2_GATE             60
+#define IMX27_CLK_PER1_GATE             61
+#define IMX27_CLK_USB_AHB_GATE          62
+#define IMX27_CLK_SLCDC_AHB_GATE        63
+#define IMX27_CLK_SAHARA_AHB_GATE       64
+#define IMX27_CLK_LCDC_AHB_GATE         65
+#define IMX27_CLK_VPU_AHB_GATE          66
+#define IMX27_CLK_FEC_AHB_GATE          67
+#define IMX27_CLK_EMMA_AHB_GATE         68
+#define IMX27_CLK_EMI_AHB_GATE          69
+#define IMX27_CLK_DMA_AHB_GATE          70
+#define IMX27_CLK_CSI_AHB_GATE          71
+#define IMX27_CLK_BROM_AHB_GATE         72
+#define IMX27_CLK_ATA_AHB_GATE          73
+#define IMX27_CLK_WDOG_IPG_GATE         74
+#define IMX27_CLK_USB_IPG_GATE          75
+#define IMX27_CLK_UART6_IPG_GATE        76
+#define IMX27_CLK_UART5_IPG_GATE        77
+#define IMX27_CLK_UART4_IPG_GATE        78
+#define IMX27_CLK_UART3_IPG_GATE        79
+#define IMX27_CLK_UART2_IPG_GATE        80
+#define IMX27_CLK_UART1_IPG_GATE        81
+#define IMX27_CLK_CKIH_DIV1P5           82
+#define IMX27_CLK_FPM                   83
+#define IMX27_CLK_MPLL_OSC_SEL          84
+#define IMX27_CLK_MPLL_SEL              85
+#define IMX27_CLK_SPLL_GATE             86
+#define IMX27_CLK_MSHC_DIV              87
+#define IMX27_CLK_RTIC_IPG_GATE         88
+#define IMX27_CLK_MSHC_IPG_GATE         89
+#define IMX27_CLK_RTIC_AHB_GATE         90
+#define IMX27_CLK_MSHC_BAUD_GATE        91
+#define IMX27_CLK_CKIH_GATE             92
+#define IMX27_CLK_MAX                   93
+#endif
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
new file mode 100644
index 000000000000..654151e24288
--- /dev/null
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
+#define __DT_BINDINGS_CLOCK_IMX6QDL_H
+#define IMX6QDL_CLK_DUMMY                       0
+#define IMX6QDL_CLK_CKIL                        1
+#define IMX6QDL_CLK_CKIH                        2
+#define IMX6QDL_CLK_OSC                         3
+#define IMX6QDL_CLK_PLL2_PFD0_352M              4
+#define IMX6QDL_CLK_PLL2_PFD1_594M              5
+#define IMX6QDL_CLK_PLL2_PFD2_396M              6
+#define IMX6QDL_CLK_PLL3_PFD0_720M              7
+#define IMX6QDL_CLK_PLL3_PFD1_540M              8
+#define IMX6QDL_CLK_PLL3_PFD2_508M              9
+#define IMX6QDL_CLK_PLL3_PFD3_454M              10
+#define IMX6QDL_CLK_PLL2_198M                   11
+#define IMX6QDL_CLK_PLL3_120M                   12
+#define IMX6QDL_CLK_PLL3_80M                    13
+#define IMX6QDL_CLK_PLL3_60M                    14
+#define IMX6QDL_CLK_TWD                         15
+#define IMX6QDL_CLK_STEP                        16
+#define IMX6QDL_CLK_PLL1_SW                     17
+#define IMX6QDL_CLK_PERIPH_PRE                  18
+#define IMX6QDL_CLK_PERIPH2_PRE                 19
+#define IMX6QDL_CLK_PERIPH_CLK2_SEL             20
+#define IMX6QDL_CLK_PERIPH2_CLK2_SEL            21
+#define IMX6QDL_CLK_AXI_SEL                     22
+#define IMX6QDL_CLK_ESAI_SEL                    23
+#define IMX6QDL_CLK_ASRC_SEL                    24
+#define IMX6QDL_CLK_SPDIF_SEL                   25
+#define IMX6QDL_CLK_GPU2D_AXI                   26
+#define IMX6QDL_CLK_GPU3D_AXI                   27
+#define IMX6QDL_CLK_GPU2D_CORE_SEL              28
+#define IMX6QDL_CLK_GPU3D_CORE_SEL              29
+#define IMX6QDL_CLK_GPU3D_SHADER_SEL            30
+#define IMX6QDL_CLK_IPU1_SEL                    31
+#define IMX6QDL_CLK_IPU2_SEL                    32
+#define IMX6QDL_CLK_LDB_DI0_SEL                 33
+#define IMX6QDL_CLK_LDB_DI1_SEL                 34
+#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL            35
+#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL            36
+#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL            37
+#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL            38
+#define IMX6QDL_CLK_IPU1_DI0_SEL                39
+#define IMX6QDL_CLK_IPU1_DI1_SEL                40
+#define IMX6QDL_CLK_IPU2_DI0_SEL                41
+#define IMX6QDL_CLK_IPU2_DI1_SEL                42
+#define IMX6QDL_CLK_HSI_TX_SEL                  43
+#define IMX6QDL_CLK_PCIE_AXI_SEL                44
+#define IMX6QDL_CLK_SSI1_SEL                    45
+#define IMX6QDL_CLK_SSI2_SEL                    46
+#define IMX6QDL_CLK_SSI3_SEL                    47
+#define IMX6QDL_CLK_USDHC1_SEL                  48
+#define IMX6QDL_CLK_USDHC2_SEL                  49
+#define IMX6QDL_CLK_USDHC3_SEL                  50
+#define IMX6QDL_CLK_USDHC4_SEL                  51
+#define IMX6QDL_CLK_ENFC_SEL                    52
+#define IMX6QDL_CLK_EMI_SEL                     53
+#define IMX6QDL_CLK_EMI_SLOW_SEL                54
+#define IMX6QDL_CLK_VDO_AXI_SEL                 55
+#define IMX6QDL_CLK_VPU_AXI_SEL                 56
+#define IMX6QDL_CLK_CKO1_SEL                    57
+#define IMX6QDL_CLK_PERIPH                      58
+#define IMX6QDL_CLK_PERIPH2                     59
+#define IMX6QDL_CLK_PERIPH_CLK2                 60
+#define IMX6QDL_CLK_PERIPH2_CLK2                61
+#define IMX6QDL_CLK_IPG                         62
+#define IMX6QDL_CLK_IPG_PER                     63
+#define IMX6QDL_CLK_ESAI_PRED                   64
+#define IMX6QDL_CLK_ESAI_PODF                   65
+#define IMX6QDL_CLK_ASRC_PRED                   66
+#define IMX6QDL_CLK_ASRC_PODF                   67
+#define IMX6QDL_CLK_SPDIF_PRED                  68
+#define IMX6QDL_CLK_SPDIF_PODF                  69
+#define IMX6QDL_CLK_CAN_ROOT                    70
+#define IMX6QDL_CLK_ECSPI_ROOT                  71
+#define IMX6QDL_CLK_GPU2D_CORE_PODF             72
+#define IMX6QDL_CLK_GPU3D_CORE_PODF             73
+#define IMX6QDL_CLK_GPU3D_SHADER                74
+#define IMX6QDL_CLK_IPU1_PODF                   75
+#define IMX6QDL_CLK_IPU2_PODF                   76
+#define IMX6QDL_CLK_LDB_DI0_PODF                77
+#define IMX6QDL_CLK_LDB_DI1_PODF                78
+#define IMX6QDL_CLK_IPU1_DI0_PRE                79
+#define IMX6QDL_CLK_IPU1_DI1_PRE                80
+#define IMX6QDL_CLK_IPU2_DI0_PRE                81
+#define IMX6QDL_CLK_IPU2_DI1_PRE                82
+#define IMX6QDL_CLK_HSI_TX_PODF                 83
+#define IMX6QDL_CLK_SSI1_PRED                   84
+#define IMX6QDL_CLK_SSI1_PODF                   85
+#define IMX6QDL_CLK_SSI2_PRED                   86
+#define IMX6QDL_CLK_SSI2_PODF                   87
+#define IMX6QDL_CLK_SSI3_PRED                   88
+#define IMX6QDL_CLK_SSI3_PODF                   89
+#define IMX6QDL_CLK_UART_SERIAL_PODF            90
+#define IMX6QDL_CLK_USDHC1_PODF                 91
+#define IMX6QDL_CLK_USDHC2_PODF                 92
+#define IMX6QDL_CLK_USDHC3_PODF                 93
+#define IMX6QDL_CLK_USDHC4_PODF                 94
+#define IMX6QDL_CLK_ENFC_PRED                   95
+#define IMX6QDL_CLK_ENFC_PODF                   96
+#define IMX6QDL_CLK_EMI_PODF                    97
+#define IMX6QDL_CLK_EMI_SLOW_PODF               98
+#define IMX6QDL_CLK_VPU_AXI_PODF                99
+#define IMX6QDL_CLK_CKO1_PODF                   100
+#define IMX6QDL_CLK_AXI                         101
+#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF           102
+#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF           103
+#define IMX6QDL_CLK_ARM                         104
+#define IMX6QDL_CLK_AHB                         105
+#define IMX6QDL_CLK_APBH_DMA                    106
+#define IMX6QDL_CLK_ASRC                        107
+#define IMX6QDL_CLK_CAN1_IPG                    108
+#define IMX6QDL_CLK_CAN1_SERIAL                 109
+#define IMX6QDL_CLK_CAN2_IPG                    110
+#define IMX6QDL_CLK_CAN2_SERIAL                 111
+#define IMX6QDL_CLK_ECSPI1                      112
+#define IMX6QDL_CLK_ECSPI2                      113
+#define IMX6QDL_CLK_ECSPI3                      114
+#define IMX6QDL_CLK_ECSPI4                      115
+#define IMX6Q_CLK_ECSPI5                        116
+#define IMX6DL_CLK_I2C4                         116
+#define IMX6QDL_CLK_ENET                        117
+#define IMX6QDL_CLK_ESAI                        118
+#define IMX6QDL_CLK_GPT_IPG                     119
+#define IMX6QDL_CLK_GPT_IPG_PER                 120
+#define IMX6QDL_CLK_GPU2D_CORE                  121
+#define IMX6QDL_CLK_GPU3D_CORE                  122
+#define IMX6QDL_CLK_HDMI_IAHB                   123
+#define IMX6QDL_CLK_HDMI_ISFR                   124
+#define IMX6QDL_CLK_I2C1                        125
+#define IMX6QDL_CLK_I2C2                        126
+#define IMX6QDL_CLK_I2C3                        127
+#define IMX6QDL_CLK_IIM                         128
+#define IMX6QDL_CLK_ENFC                        129
+#define IMX6QDL_CLK_IPU1                        130
+#define IMX6QDL_CLK_IPU1_DI0                    131
+#define IMX6QDL_CLK_IPU1_DI1                    132
+#define IMX6QDL_CLK_IPU2                        133
+#define IMX6QDL_CLK_IPU2_DI0                    134
+#define IMX6QDL_CLK_LDB_DI0                     135
+#define IMX6QDL_CLK_LDB_DI1                     136
+#define IMX6QDL_CLK_IPU2_DI1                    137
+#define IMX6QDL_CLK_HSI_TX                      138
+#define IMX6QDL_CLK_MLB                         139
+#define IMX6QDL_CLK_MMDC_CH0_AXI                140
+#define IMX6QDL_CLK_MMDC_CH1_AXI                141
+#define IMX6QDL_CLK_OCRAM                       142
+#define IMX6QDL_CLK_OPENVG_AXI                  143
+#define IMX6QDL_CLK_PCIE_AXI                    144
+#define IMX6QDL_CLK_PWM1                        145
+#define IMX6QDL_CLK_PWM2                        146
+#define IMX6QDL_CLK_PWM3                        147
+#define IMX6QDL_CLK_PWM4                        148
+#define IMX6QDL_CLK_PER1_BCH                    149
+#define IMX6QDL_CLK_GPMI_BCH_APB                150
+#define IMX6QDL_CLK_GPMI_BCH                    151
+#define IMX6QDL_CLK_GPMI_IO                     152
+#define IMX6QDL_CLK_GPMI_APB                    153
+#define IMX6QDL_CLK_SATA                        154
+#define IMX6QDL_CLK_SDMA                        155
+#define IMX6QDL_CLK_SPBA                        156
+#define IMX6QDL_CLK_SSI1                        157
+#define IMX6QDL_CLK_SSI2                        158
+#define IMX6QDL_CLK_SSI3                        159
+#define IMX6QDL_CLK_UART_IPG                    160
+#define IMX6QDL_CLK_UART_SERIAL                 161
+#define IMX6QDL_CLK_USBOH3                      162
+#define IMX6QDL_CLK_USDHC1                      163
+#define IMX6QDL_CLK_USDHC2                      164
+#define IMX6QDL_CLK_USDHC3                      165
+#define IMX6QDL_CLK_USDHC4                      166
+#define IMX6QDL_CLK_VDO_AXI                     167
+#define IMX6QDL_CLK_VPU_AXI                     168
+#define IMX6QDL_CLK_CKO1                        169
+#define IMX6QDL_CLK_PLL1_SYS                    170
+#define IMX6QDL_CLK_PLL2_BUS                    171
+#define IMX6QDL_CLK_PLL3_USB_OTG                172
+#define IMX6QDL_CLK_PLL4_AUDIO                  173
+#define IMX6QDL_CLK_PLL5_VIDEO                  174
+#define IMX6QDL_CLK_PLL8_MLB                    175
+#define IMX6QDL_CLK_PLL7_USB_HOST               176
+#define IMX6QDL_CLK_PLL6_ENET                   177
+#define IMX6QDL_CLK_SSI1_IPG                    178
+#define IMX6QDL_CLK_SSI2_IPG                    179
+#define IMX6QDL_CLK_SSI3_IPG                    180
+#define IMX6QDL_CLK_ROM                         181
+#define IMX6QDL_CLK_USBPHY1                     182
+#define IMX6QDL_CLK_USBPHY2                     183
+#define IMX6QDL_CLK_LDB_DI0_DIV_3_5             184
+#define IMX6QDL_CLK_LDB_DI1_DIV_3_5             185
+#define IMX6QDL_CLK_SATA_REF                    186
+#define IMX6QDL_CLK_SATA_REF_100M               187
+#define IMX6QDL_CLK_PCIE_REF                    188
+#define IMX6QDL_CLK_PCIE_REF_125M               189
+#define IMX6QDL_CLK_ENET_REF                    190
+#define IMX6QDL_CLK_USBPHY1_GATE                191
+#define IMX6QDL_CLK_USBPHY2_GATE                192
+#define IMX6QDL_CLK_PLL4_POST_DIV               193
+#define IMX6QDL_CLK_PLL5_POST_DIV               194
+#define IMX6QDL_CLK_PLL5_VIDEO_DIV              195
+#define IMX6QDL_CLK_EIM_SLOW                    196
+#define IMX6QDL_CLK_SPDIF                       197
+#define IMX6QDL_CLK_CKO2_SEL                    198
+#define IMX6QDL_CLK_CKO2_PODF                   199
+#define IMX6QDL_CLK_CKO2                        200
+#define IMX6QDL_CLK_CKO                         201
+#define IMX6QDL_CLK_VDOA                        202
+#define IMX6QDL_CLK_PLL4_AUDIO_DIV              203
+#define IMX6QDL_CLK_LVDS1_SEL                   204
+#define IMX6QDL_CLK_LVDS2_SEL                   205
+#define IMX6QDL_CLK_LVDS1_GATE                  206
+#define IMX6QDL_CLK_LVDS2_GATE                  207
+#define IMX6QDL_CLK_ESAI_AHB                    208
+#define IMX6QDL_CLK_END                         209
+#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-apq8084.h b/include/dt-bindings/clock/qcom,gcc-apq8084.h
new file mode 100644
index 000000000000..2c0da566c46a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-apq8084.h
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H
+#define _DT_BINDINGS_CLK_APQ_GCC_8084_H
+#define GPLL0                                           0
+#define GPLL0_VOTE                                      1
+#define GPLL1                                           2
+#define GPLL1_VOTE                                      3
+#define GPLL2                                           4
+#define GPLL2_VOTE                                      5
+#define GPLL3                                           6
+#define GPLL3_VOTE                                      7
+#define GPLL4                                           8
+#define GPLL4_VOTE                                      9
+#define CONFIG_NOC_CLK_SRC                              10
+#define PERIPH_NOC_CLK_SRC                              11
+#define SYSTEM_NOC_CLK_SRC                              12
+#define BLSP_UART_SIM_CLK_SRC                           13
+#define QDSS_TSCTR_CLK_SRC                              14
+#define UFS_AXI_CLK_SRC                                 15
+#define RPM_CLK_SRC                                     16
+#define KPSS_AHB_CLK_SRC                                17
+#define QDSS_AT_CLK_SRC                                 18
+#define BIMC_DDR_CLK_SRC                                19
+#define USB30_MASTER_CLK_SRC                            20
+#define USB30_SEC_MASTER_CLK_SRC                        21
+#define USB_HSIC_AHB_CLK_SRC                            22
+#define MMSS_BIMC_GFX_CLK_SRC                           23
+#define QDSS_STM_CLK_SRC                                24
+#define ACC_CLK_SRC                                     25
+#define SEC_CTRL_CLK_SRC                                26
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC                     27
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC                     28
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC                     29
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC                     30
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC                     31
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC                     32
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC                     33
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC                     34
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC                     35
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC                     36
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC                     37
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC                     38
+#define BLSP1_UART1_APPS_CLK_SRC                        39
+#define BLSP1_UART2_APPS_CLK_SRC                        40
+#define BLSP1_UART3_APPS_CLK_SRC                        41
+#define BLSP1_UART4_APPS_CLK_SRC                        42
+#define BLSP1_UART5_APPS_CLK_SRC                        43
+#define BLSP1_UART6_APPS_CLK_SRC                        44
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC                     45
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC                     46
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC                     47
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC                     48
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC                     49
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC                     50
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC                     51
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC                     52
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC                     53
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC                     54
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC                     55
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC                     56
+#define BLSP2_UART1_APPS_CLK_SRC                        57
+#define BLSP2_UART2_APPS_CLK_SRC                        58
+#define BLSP2_UART3_APPS_CLK_SRC                        59
+#define BLSP2_UART4_APPS_CLK_SRC                        60
+#define BLSP2_UART5_APPS_CLK_SRC                        61
+#define BLSP2_UART6_APPS_CLK_SRC                        62
+#define CE1_CLK_SRC                                     63
+#define CE2_CLK_SRC                                     64
+#define CE3_CLK_SRC                                     65
+#define GP1_CLK_SRC                                     66
+#define GP2_CLK_SRC                                     67
+#define GP3_CLK_SRC                                     68
+#define PDM2_CLK_SRC                                    69
+#define QDSS_TRACECLKIN_CLK_SRC                         70
+#define RBCPR_CLK_SRC                                   71
+#define SATA_ASIC0_CLK_SRC                              72
+#define SATA_PMALIVE_CLK_SRC                            73
+#define SATA_RX_CLK_SRC                                 74
+#define SATA_RX_OOB_CLK_SRC                             75
+#define SDCC1_APPS_CLK_SRC                              76
+#define SDCC2_APPS_CLK_SRC                              77
+#define SDCC3_APPS_CLK_SRC                              78
+#define SDCC4_APPS_CLK_SRC                              79
+#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK                   80
+#define SPMI_AHB_CLK_SRC                                81
+#define SPMI_SER_CLK_SRC                                82
+#define TSIF_REF_CLK_SRC                                83
+#define USB30_MOCK_UTMI_CLK_SRC                         84
+#define USB30_SEC_MOCK_UTMI_CLK_SRC                     85
+#define USB_HS_SYSTEM_CLK_SRC                           86
+#define USB_HSIC_CLK_SRC                                87
+#define USB_HSIC_IO_CAL_CLK_SRC                         88
+#define USB_HSIC_MOCK_UTMI_CLK_SRC                      89
+#define USB_HSIC_SYSTEM_CLK_SRC                         90
+#define GCC_BAM_DMA_AHB_CLK                             91
+#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK               92
+#define DDR_CLK_SRC                                     93
+#define GCC_BIMC_CFG_AHB_CLK                            94
+#define GCC_BIMC_CLK                                    95
+#define GCC_BIMC_KPSS_AXI_CLK                           96
+#define GCC_BIMC_SLEEP_CLK                              97
+#define GCC_BIMC_SYSNOC_AXI_CLK                         98
+#define GCC_BIMC_XO_CLK                                 99
+#define GCC_BLSP1_AHB_CLK                               100
+#define GCC_BLSP1_SLEEP_CLK                             101
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK                     102
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK                     103
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK                     104
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK                     105
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK                     106
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK                     107
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK                     108
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK                     109
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK                     110
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK                     111
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK                     112
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK                     113
+#define GCC_BLSP1_UART1_APPS_CLK                        114
+#define GCC_BLSP1_UART1_SIM_CLK                         115
+#define GCC_BLSP1_UART2_APPS_CLK                        116
+#define GCC_BLSP1_UART2_SIM_CLK                         117
+#define GCC_BLSP1_UART3_APPS_CLK                        118
+#define GCC_BLSP1_UART3_SIM_CLK                         119
+#define GCC_BLSP1_UART4_APPS_CLK                        120
+#define GCC_BLSP1_UART4_SIM_CLK                         121
+#define GCC_BLSP1_UART5_APPS_CLK                        122
+#define GCC_BLSP1_UART5_SIM_CLK                         123
+#define GCC_BLSP1_UART6_APPS_CLK                        124
+#define GCC_BLSP1_UART6_SIM_CLK                         125
+#define GCC_BLSP2_AHB_CLK                               126
+#define GCC_BLSP2_SLEEP_CLK                             127
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK                     128
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK                     129
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK                     130
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK                     131
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK                     132
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK                     133
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK                     134
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK                     135
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK                     136
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK                     137
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK                     138
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK                     139
+#define GCC_BLSP2_UART1_APPS_CLK                        140
+#define GCC_BLSP2_UART1_SIM_CLK                         141
+#define GCC_BLSP2_UART2_APPS_CLK                        142
+#define GCC_BLSP2_UART2_SIM_CLK                         143
+#define GCC_BLSP2_UART3_APPS_CLK                        144
+#define GCC_BLSP2_UART3_SIM_CLK                         145
+#define GCC_BLSP2_UART4_APPS_CLK                        146
+#define GCC_BLSP2_UART4_SIM_CLK                         147
+#define GCC_BLSP2_UART5_APPS_CLK                        148
+#define GCC_BLSP2_UART5_SIM_CLK                         149
+#define GCC_BLSP2_UART6_APPS_CLK                        150
+#define GCC_BLSP2_UART6_SIM_CLK                         151
+#define GCC_BOOT_ROM_AHB_CLK                            152
+#define GCC_CE1_AHB_CLK                                 153
+#define GCC_CE1_AXI_CLK                                 154
+#define GCC_CE1_CLK                                     155
+#define GCC_CE2_AHB_CLK                                 156
+#define GCC_CE2_AXI_CLK                                 157
+#define GCC_CE2_CLK                                     158
+#define GCC_CE3_AHB_CLK                                 159
+#define GCC_CE3_AXI_CLK                                 160
+#define GCC_CE3_CLK                                     161
+#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK                   162
+#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK                   163
+#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK                   164
+#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK                   165
+#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK                   166
+#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK                   167
+#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK                   168
+#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK                   169
+#define GCC_CFG_NOC_AHB_CLK                             170
+#define GCC_CFG_NOC_DDR_CFG_CLK                         171
+#define GCC_CFG_NOC_RPM_AHB_CLK                         172
+#define GCC_COPSS_SMMU_AHB_CLK                          173
+#define GCC_COPSS_SMMU_AXI_CLK                          174
+#define GCC_DCD_XO_CLK                                  175
+#define GCC_BIMC_DDR_CH0_CLK                            176
+#define GCC_BIMC_DDR_CH1_CLK                            177
+#define GCC_BIMC_DDR_CPLL0_CLK                          178
+#define GCC_BIMC_DDR_CPLL1_CLK                          179
+#define GCC_BIMC_GFX_CLK                                180
+#define GCC_DDR_DIM_CFG_CLK                             181
+#define GCC_DDR_DIM_SLEEP_CLK                           182
+#define GCC_DEHR_CLK                                    183
+#define GCC_AHB_CLK                                     184
+#define GCC_IM_SLEEP_CLK                                185
+#define GCC_XO_CLK                                      186
+#define GCC_XO_DIV4_CLK                                 187
+#define GCC_GP1_CLK                                     188
+#define GCC_GP2_CLK                                     189
+#define GCC_GP3_CLK                                     190
+#define GCC_IMEM_AXI_CLK                                191
+#define GCC_IMEM_CFG_AHB_CLK                            192
+#define GCC_KPSS_AHB_CLK                                193
+#define GCC_KPSS_AXI_CLK                                194
+#define GCC_LPASS_MPORT_AXI_CLK                         195
+#define GCC_LPASS_Q6_AXI_CLK                            196
+#define GCC_LPASS_SWAY_CLK                              197
+#define GCC_MMSS_BIMC_GFX_CLK                           198
+#define GCC_MMSS_NOC_AT_CLK                             199
+#define GCC_MMSS_NOC_CFG_AHB_CLK                        200
+#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK              201
+#define GCC_OCMEM_NOC_CFG_AHB_CLK                       202
+#define GCC_OCMEM_SYS_NOC_AXI_CLK                       203
+#define GCC_MPM_AHB_CLK                                 204
+#define GCC_MSG_RAM_AHB_CLK                             205
+#define GCC_NOC_CONF_XPU_AHB_CLK                        206
+#define GCC_PDM2_CLK                                    207
+#define GCC_PDM_AHB_CLK                                 208
+#define GCC_PDM_XO4_CLK                                 209
+#define GCC_PERIPH_NOC_AHB_CLK                          210
+#define GCC_PERIPH_NOC_AT_CLK                           211
+#define GCC_PERIPH_NOC_CFG_AHB_CLK                      212
+#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK                 213
+#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK                  214
+#define GCC_PERIPH_XPU_AHB_CLK                          215
+#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK                   216
+#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK                   217
+#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK                   218
+#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK                   219
+#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK                   220
+#define GCC_PRNG_AHB_CLK                                221
+#define GCC_QDSS_AT_CLK                                 222
+#define GCC_QDSS_CFG_AHB_CLK                            223
+#define GCC_QDSS_DAP_AHB_CLK                            224
+#define GCC_QDSS_DAP_CLK                                225
+#define GCC_QDSS_ETR_USB_CLK                            226
+#define GCC_QDSS_STM_CLK                                227
+#define GCC_QDSS_TRACECLKIN_CLK                         228
+#define GCC_QDSS_TSCTR_DIV16_CLK                        229
+#define GCC_QDSS_TSCTR_DIV2_CLK                         230
+#define GCC_QDSS_TSCTR_DIV3_CLK                         231
+#define GCC_QDSS_TSCTR_DIV4_CLK                         232
+#define GCC_QDSS_TSCTR_DIV8_CLK                         233
+#define GCC_QDSS_RBCPR_XPU_AHB_CLK                      234
+#define GCC_RBCPR_AHB_CLK                               235
+#define GCC_RBCPR_CLK                                   236
+#define GCC_RPM_BUS_AHB_CLK                             237
+#define GCC_RPM_PROC_HCLK                               238
+#define GCC_RPM_SLEEP_CLK                               239
+#define GCC_RPM_TIMER_CLK                               240
+#define GCC_SATA_ASIC0_CLK                              241
+#define GCC_SATA_AXI_CLK                                242
+#define GCC_SATA_CFG_AHB_CLK                            243
+#define GCC_SATA_PMALIVE_CLK                            244
+#define GCC_SATA_RX_CLK                                 245
+#define GCC_SATA_RX_OOB_CLK                             246
+#define GCC_SDCC1_AHB_CLK                               247
+#define GCC_SDCC1_APPS_CLK                              248
+#define GCC_SDCC1_CDCCAL_FF_CLK                         249
+#define GCC_SDCC1_CDCCAL_SLEEP_CLK                      250
+#define GCC_SDCC2_AHB_CLK                               251
+#define GCC_SDCC2_APPS_CLK                              252
+#define GCC_SDCC2_INACTIVITY_TIMERS_CLK                 253
+#define GCC_SDCC3_AHB_CLK                               254
+#define GCC_SDCC3_APPS_CLK                              255
+#define GCC_SDCC3_INACTIVITY_TIMERS_CLK                 256
+#define GCC_SDCC4_AHB_CLK                               257
+#define GCC_SDCC4_APPS_CLK                              258
+#define GCC_SDCC4_INACTIVITY_TIMERS_CLK                 259
+#define GCC_SEC_CTRL_ACC_CLK                            260
+#define GCC_SEC_CTRL_AHB_CLK                            261
+#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK                 262
+#define GCC_SEC_CTRL_CLK                                263
+#define GCC_SEC_CTRL_SENSE_CLK                          264
+#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK                   265
+#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK                   266
+#define GCC_SPDM_BIMC_CY_CLK                            267
+#define GCC_SPDM_CFG_AHB_CLK                            268
+#define GCC_SPDM_DEBUG_CY_CLK                           269
+#define GCC_SPDM_FF_CLK                                 270
+#define GCC_SPDM_MSTR_AHB_CLK                           271
+#define GCC_SPDM_PNOC_CY_CLK                            272
+#define GCC_SPDM_RPM_CY_CLK                             273
+#define GCC_SPDM_SNOC_CY_CLK                            274
+#define GCC_SPMI_AHB_CLK                                275
+#define GCC_SPMI_CNOC_AHB_CLK                           276
+#define GCC_SPMI_SER_CLK                                277
+#define GCC_SPSS_AHB_CLK                                278
+#define GCC_SNOC_CNOC_AHB_CLK                           279
+#define GCC_SNOC_PNOC_AHB_CLK                           280
+#define GCC_SYS_NOC_AT_CLK                              281
+#define GCC_SYS_NOC_AXI_CLK                             282
+#define GCC_SYS_NOC_KPSS_AHB_CLK                        283
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK                    284
+#define GCC_SYS_NOC_UFS_AXI_CLK                         285
+#define GCC_SYS_NOC_USB3_AXI_CLK                        286
+#define GCC_SYS_NOC_USB3_SEC_AXI_CLK                    287
+#define GCC_TCSR_AHB_CLK                                288
+#define GCC_TLMM_AHB_CLK                                289
+#define GCC_TLMM_CLK                                    290
+#define GCC_TSIF_AHB_CLK                                291
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK                  292
+#define GCC_TSIF_REF_CLK                                293
+#define GCC_UFS_AHB_CLK                                 294
+#define GCC_UFS_AXI_CLK                                 295
+#define GCC_UFS_RX_CFG_CLK                              296
+#define GCC_UFS_RX_SYMBOL_0_CLK                         297
+#define GCC_UFS_RX_SYMBOL_1_CLK                         298
+#define GCC_UFS_TX_CFG_CLK                              299
+#define GCC_UFS_TX_SYMBOL_0_CLK                         300
+#define GCC_UFS_TX_SYMBOL_1_CLK                         301
+#define GCC_USB2A_PHY_SLEEP_CLK                         302
+#define GCC_USB2B_PHY_SLEEP_CLK                         303
+#define GCC_USB30_MASTER_CLK                            304
+#define GCC_USB30_MOCK_UTMI_CLK                         305
+#define GCC_USB30_SLEEP_CLK                             306
+#define GCC_USB30_SEC_MASTER_CLK                        307
+#define GCC_USB30_SEC_MOCK_UTMI_CLK                     308
+#define GCC_USB30_SEC_SLEEP_CLK                         309
+#define GCC_USB_HS_AHB_CLK                              310
+#define GCC_USB_HS_INACTIVITY_TIMERS_CLK                311
+#define GCC_USB_HS_SYSTEM_CLK                           312
+#define GCC_USB_HSIC_AHB_CLK                            313
+#define GCC_USB_HSIC_CLK                                314
+#define GCC_USB_HSIC_IO_CAL_CLK                         315
+#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK                   316
+#define GCC_USB_HSIC_MOCK_UTMI_CLK                      317
+#define GCC_USB_HSIC_SYSTEM_CLK                         318
+#define PCIE_0_AUX_CLK_SRC                              319
+#define PCIE_0_PIPE_CLK_SRC                             320
+#define PCIE_1_AUX_CLK_SRC                              321
+#define PCIE_1_PIPE_CLK_SRC                             322
+#define GCC_PCIE_0_AUX_CLK                              323
+#define GCC_PCIE_0_CFG_AHB_CLK                          324
+#define GCC_PCIE_0_MSTR_AXI_CLK                         325
+#define GCC_PCIE_0_PIPE_CLK                             326
+#define GCC_PCIE_0_SLV_AXI_CLK                          327
+#define GCC_PCIE_1_AUX_CLK                              328
+#define GCC_PCIE_1_CFG_AHB_CLK                          329
+#define GCC_PCIE_1_MSTR_AXI_CLK                         330
+#define GCC_PCIE_1_PIPE_CLK                             331
+#define GCC_PCIE_1_SLV_AXI_CLK                          332
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
new file mode 100644
index 000000000000..b857cadb0bd4
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
+#define _DT_BINDINGS_CLK_GCC_IPQ806X_H
+#define AFAB_CLK_SRC                            0
+#define QDSS_STM_CLK                            1
+#define SCSS_A_CLK                              2
+#define SCSS_H_CLK                              3
+#define AFAB_CORE_CLK                           4
+#define SCSS_XO_SRC_CLK                         5
+#define AFAB_EBI1_CH0_A_CLK                     6
+#define AFAB_EBI1_CH1_A_CLK                     7
+#define AFAB_AXI_S0_FCLK                        8
+#define AFAB_AXI_S1_FCLK                        9
+#define AFAB_AXI_S2_FCLK                        10
+#define AFAB_AXI_S3_FCLK                        11
+#define AFAB_AXI_S4_FCLK                        12
+#define SFAB_CORE_CLK                           13
+#define SFAB_AXI_S0_FCLK                        14
+#define SFAB_AXI_S1_FCLK                        15
+#define SFAB_AXI_S2_FCLK                        16
+#define SFAB_AXI_S3_FCLK                        17
+#define SFAB_AXI_S4_FCLK                        18
+#define SFAB_AXI_S5_FCLK                        19
+#define SFAB_AHB_S0_FCLK                        20
+#define SFAB_AHB_S1_FCLK                        21
+#define SFAB_AHB_S2_FCLK                        22
+#define SFAB_AHB_S3_FCLK                        23
+#define SFAB_AHB_S4_FCLK                        24
+#define SFAB_AHB_S5_FCLK                        25
+#define SFAB_AHB_S6_FCLK                        26
+#define SFAB_AHB_S7_FCLK                        27
+#define QDSS_AT_CLK_SRC                         28
+#define QDSS_AT_CLK                             29
+#define QDSS_TRACECLKIN_CLK_SRC                 30
+#define QDSS_TRACECLKIN_CLK                     31
+#define QDSS_TSCTR_CLK_SRC                      32
+#define QDSS_TSCTR_CLK                          33
+#define SFAB_ADM0_M0_A_CLK                      34
+#define SFAB_ADM0_M1_A_CLK                      35
+#define SFAB_ADM0_M2_H_CLK                      36
+#define ADM0_CLK                                37
+#define ADM0_PBUS_CLK                           38
+#define IMEM0_A_CLK                             39
+#define QDSS_H_CLK                              40
+#define PCIE_A_CLK                              41
+#define PCIE_AUX_CLK                            42
+#define PCIE_H_CLK                              43
+#define PCIE_PHY_CLK                            44
+#define SFAB_CLK_SRC                            45
+#define SFAB_LPASS_Q6_A_CLK                     46
+#define SFAB_AFAB_M_A_CLK                       47
+#define AFAB_SFAB_M0_A_CLK                      48
+#define AFAB_SFAB_M1_A_CLK                      49
+#define SFAB_SATA_S_H_CLK                       50
+#define DFAB_CLK_SRC                            51
+#define DFAB_CLK                                52
+#define SFAB_DFAB_M_A_CLK                       53
+#define DFAB_SFAB_M_A_CLK                       54
+#define DFAB_SWAY0_H_CLK                        55
+#define DFAB_SWAY1_H_CLK                        56
+#define DFAB_ARB0_H_CLK                         57
+#define DFAB_ARB1_H_CLK                         58
+#define PPSS_H_CLK                              59
+#define PPSS_PROC_CLK                           60
+#define PPSS_TIMER0_CLK                         61
+#define PPSS_TIMER1_CLK                         62
+#define PMEM_A_CLK                              63
+#define DMA_BAM_H_CLK                           64
+#define SIC_H_CLK                               65
+#define SPS_TIC_H_CLK                           66
+#define CFPB_2X_CLK_SRC                         67
+#define CFPB_CLK                                68
+#define CFPB0_H_CLK                             69
+#define CFPB1_H_CLK                             70
+#define CFPB2_H_CLK                             71
+#define SFAB_CFPB_M_H_CLK                       72
+#define CFPB_MASTER_H_CLK                       73
+#define SFAB_CFPB_S_H_CLK                       74
+#define CFPB_SPLITTER_H_CLK                     75
+#define TSIF_H_CLK                              76
+#define TSIF_INACTIVITY_TIMERS_CLK              77
+#define TSIF_REF_SRC                            78
+#define TSIF_REF_CLK                            79
+#define CE1_H_CLK                               80
+#define CE1_CORE_CLK                            81
+#define CE1_SLEEP_CLK                           82
+#define CE2_H_CLK                               83
+#define CE2_CORE_CLK                            84
+#define SFPB_H_CLK_SRC                          85
+#define SFPB_H_CLK                              86
+#define SFAB_SFPB_M_H_CLK                       87
+#define SFAB_SFPB_S_H_CLK                       88
+#define RPM_PROC_CLK                            89
+#define RPM_BUS_H_CLK                           90
+#define RPM_SLEEP_CLK                           91
+#define RPM_TIMER_CLK                           92
+#define RPM_MSG_RAM_H_CLK                       93
+#define PMIC_ARB0_H_CLK                         94
+#define PMIC_ARB1_H_CLK                         95
+#define PMIC_SSBI2_SRC                          96
+#define PMIC_SSBI2_CLK                          97
+#define SDC1_H_CLK                              98
+#define SDC2_H_CLK                              99
+#define SDC3_H_CLK                              100
+#define SDC4_H_CLK                              101
+#define SDC1_SRC                                102
+#define SDC1_CLK                                103
+#define SDC2_SRC                                104
+#define SDC2_CLK                                105
+#define SDC3_SRC                                106
+#define SDC3_CLK                                107
+#define SDC4_SRC                                108
+#define SDC4_CLK                                109
+#define USB_HS1_H_CLK                           110
+#define USB_HS1_XCVR_SRC                        111
+#define USB_HS1_XCVR_CLK                        112
+#define USB_HSIC_H_CLK                          113
+#define USB_HSIC_XCVR_SRC                       114
+#define USB_HSIC_XCVR_CLK                       115
+#define USB_HSIC_SYSTEM_CLK_SRC                 116
+#define USB_HSIC_SYSTEM_CLK                     117
+#define CFPB0_C0_H_CLK                          118
+#define CFPB0_D0_H_CLK                          119
+#define CFPB0_C1_H_CLK                          120
+#define CFPB0_D1_H_CLK                          121
+#define USB_FS1_H_CLK                           122
+#define USB_FS1_XCVR_SRC                        123
+#define USB_FS1_XCVR_CLK                        124
+#define USB_FS1_SYSTEM_CLK                      125
+#define GSBI_COMMON_SIM_SRC                     126
+#define GSBI1_H_CLK                             127
+#define GSBI2_H_CLK                             128
+#define GSBI3_H_CLK                             129
+#define GSBI4_H_CLK                             130
+#define GSBI5_H_CLK                             131
+#define GSBI6_H_CLK                             132
+#define GSBI7_H_CLK                             133
+#define GSBI1_QUP_SRC                           134
+#define GSBI1_QUP_CLK                           135
+#define GSBI2_QUP_SRC                           136
+#define GSBI2_QUP_CLK                           137
+#define GSBI3_QUP_SRC                           138
+#define GSBI3_QUP_CLK                           139
+#define GSBI4_QUP_SRC                           140
+#define GSBI4_QUP_CLK                           141
+#define GSBI5_QUP_SRC                           142
+#define GSBI5_QUP_CLK                           143
+#define GSBI6_QUP_SRC                           144
+#define GSBI6_QUP_CLK                           145
+#define GSBI7_QUP_SRC                           146
+#define GSBI7_QUP_CLK                           147
+#define GSBI1_UART_SRC                          148
+#define GSBI1_UART_CLK                          149
+#define GSBI2_UART_SRC                          150
+#define GSBI2_UART_CLK                          151
+#define GSBI3_UART_SRC                          152
+#define GSBI3_UART_CLK                          153
+#define GSBI4_UART_SRC                          154
+#define GSBI4_UART_CLK                          155
+#define GSBI5_UART_SRC                          156
+#define GSBI5_UART_CLK                          157
+#define GSBI6_UART_SRC                          158
+#define GSBI6_UART_CLK                          159
+#define GSBI7_UART_SRC                          160
+#define GSBI7_UART_CLK                          161
+#define GSBI1_SIM_CLK                           162
+#define GSBI2_SIM_CLK                           163
+#define GSBI3_SIM_CLK                           164
+#define GSBI4_SIM_CLK                           165
+#define GSBI5_SIM_CLK                           166
+#define GSBI6_SIM_CLK                           167
+#define GSBI7_SIM_CLK                           168
+#define USB_HSIC_HSIC_CLK_SRC                   169
+#define USB_HSIC_HSIC_CLK                       170
+#define USB_HSIC_HSIO_CAL_CLK                   171
+#define SPDM_CFG_H_CLK                          172
+#define SPDM_MSTR_H_CLK                         173
+#define SPDM_FF_CLK_SRC                         174
+#define SPDM_FF_CLK                             175
+#define SEC_CTRL_CLK                            176
+#define SEC_CTRL_ACC_CLK_SRC                    177
+#define SEC_CTRL_ACC_CLK                        178
+#define TLMM_H_CLK                              179
+#define TLMM_CLK                                180
+#define SATA_H_CLK                              181
+#define SATA_CLK_SRC                            182
+#define SATA_RXOOB_CLK                          183
+#define SATA_PMALIVE_CLK                        184
+#define SATA_PHY_REF_CLK                        185
+#define SATA_A_CLK                              186
+#define SATA_PHY_CFG_CLK                        187
+#define TSSC_CLK_SRC                            188
+#define TSSC_CLK                                189
+#define PDM_SRC                                 190
+#define PDM_CLK                                 191
+#define GP0_SRC                                 192
+#define GP0_CLK                                 193
+#define GP1_SRC                                 194
+#define GP1_CLK                                 195
+#define GP2_SRC                                 196
+#define GP2_CLK                                 197
+#define MPM_CLK                                 198
+#define EBI1_CLK_SRC                            199
+#define EBI1_CH0_CLK                            200
+#define EBI1_CH1_CLK                            201
+#define EBI1_2X_CLK                             202
+#define EBI1_CH0_DQ_CLK                         203
+#define EBI1_CH1_DQ_CLK                         204
+#define EBI1_CH0_CA_CLK                         205
+#define EBI1_CH1_CA_CLK                         206
+#define EBI1_XO_CLK                             207
+#define SFAB_SMPSS_S_H_CLK                      208
+#define PRNG_SRC                                209
+#define PRNG_CLK                                210
+#define PXO_SRC                                 211
+#define SPDM_CY_PORT0_CLK                       212
+#define SPDM_CY_PORT1_CLK                       213
+#define SPDM_CY_PORT2_CLK                       214
+#define SPDM_CY_PORT3_CLK                       215
+#define SPDM_CY_PORT4_CLK                       216
+#define SPDM_CY_PORT5_CLK                       217
+#define SPDM_CY_PORT6_CLK                       218
+#define SPDM_CY_PORT7_CLK                       219
+#define PLL0                                    220
+#define PLL0_VOTE                               221
+#define PLL3                                    222
+#define PLL3_VOTE                               223
+#define PLL4                                    224
+#define PLL4_VOTE                               225
+#define PLL8                                    226
+#define PLL8_VOTE                               227
+#define PLL9                                    228
+#define PLL10                                   229
+#define PLL11                                   230
+#define PLL12                                   231
+#define PLL14                                   232
+#define PLL14_VOTE                              233
+#define PLL18                                   234
+#define CE5_SRC                                 235
+#define CE5_H_CLK                               236
+#define CE5_CORE_CLK                            237
+#define CE3_SLEEP_CLK                           238
+#define SFAB_AHB_S8_FCLK                        239
+#define SPDM_CY_PORT8_CLK                       246
+#define PCIE_ALT_REF_SRC                        247
+#define PCIE_ALT_REF_CLK                        248
+#define PCIE_1_A_CLK                            249
+#define PCIE_1_AUX_CLK                          250
+#define PCIE_1_H_CLK                            251
+#define PCIE_1_PHY_CLK                          252
+#define PCIE_1_ALT_REF_SRC                      253
+#define PCIE_1_ALT_REF_CLK                      254
+#define PCIE_2_A_CLK                            255
+#define PCIE_2_AUX_CLK                          256
+#define PCIE_2_H_CLK                            257
+#define PCIE_2_PHY_CLK                          258
+#define PCIE_2_ALT_REF_SRC                      259
+#define PCIE_2_ALT_REF_CLK                      260
+#define EBI2_CLK                                261
+#define USB30_SLEEP_CLK                         262
+#define USB30_UTMI_SRC                          263
+#define USB30_0_UTMI_CLK                        264
+#define USB30_1_UTMI_CLK                        265
+#define USB30_MASTER_SRC                        266
+#define USB30_0_MASTER_CLK                      267
+#define USB30_1_MASTER_CLK                      268
+#define GMAC_CORE1_CLK_SRC                      269
+#define GMAC_CORE2_CLK_SRC                      270
+#define GMAC_CORE3_CLK_SRC                      271
+#define GMAC_CORE4_CLK_SRC                      272
+#define GMAC_CORE1_CLK                          273
+#define GMAC_CORE2_CLK                          274
+#define GMAC_CORE3_CLK                          275
+#define GMAC_CORE4_CLK                          276
+#define UBI32_CORE1_CLK_SRC                     277
+#define UBI32_CORE2_CLK_SRC                     278
+#define UBI32_CORE1_CLK                         279
+#define UBI32_CORE2_CLK                         280
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h
index f9f547146a15..7d20eedfee98 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
@@ -308,5 +308,16 @@
 #define PLL13                                   292
 #define PLL14                                   293
 #define PLL14_VOTE                              294
+#define USB_HS3_H_CLK                           295
+#define USB_HS3_XCVR_SRC                        296
+#define USB_HS3_XCVR_CLK                        297
+#define USB_HS4_H_CLK                           298
+#define USB_HS4_XCVR_SRC                        299
+#define USB_HS4_XCVR_CLK                        300
+#define SATA_PHY_CFG_CLK                        301
+#define SATA_A_CLK                              302
+#define CE3_SRC                                 303
+#define CE3_CORE_CLK                            304
+#define CE3_H_CLK                               305
 #endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
new file mode 100644
index 000000000000..a929f86d0ddd
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H
+#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H
+#define MMSS_AHB_CLK_SRC                0
+#define MMSS_AXI_CLK_SRC                1
+#define MMPLL0                          2
+#define MMPLL0_VOTE                     3
+#define MMPLL1                          4
+#define MMPLL1_VOTE                     5
+#define MMPLL2                          6
+#define MMPLL3                          7
+#define MMPLL4                          8
+#define CSI0_CLK_SRC                    9
+#define CSI1_CLK_SRC                    10
+#define CSI2_CLK_SRC                    11
+#define CSI3_CLK_SRC                    12
+#define VCODEC0_CLK_SRC                 13
+#define VFE0_CLK_SRC                    14
+#define VFE1_CLK_SRC                    15
+#define MDP_CLK_SRC                     16
+#define PCLK0_CLK_SRC                   17
+#define PCLK1_CLK_SRC                   18
+#define OCMEMNOC_CLK_SRC                19
+#define GFX3D_CLK_SRC                   20
+#define JPEG0_CLK_SRC                   21
+#define JPEG1_CLK_SRC                   22
+#define JPEG2_CLK_SRC                   23
+#define EDPPIXEL_CLK_SRC                24
+#define EXTPCLK_CLK_SRC                 25
+#define VP_CLK_SRC                      26
+#define CCI_CLK_SRC                     27
+#define CAMSS_GP0_CLK_SRC               28
+#define CAMSS_GP1_CLK_SRC               29
+#define MCLK0_CLK_SRC                   30
+#define MCLK1_CLK_SRC                   31
+#define MCLK2_CLK_SRC                   32
+#define MCLK3_CLK_SRC                   33
+#define CSI0PHYTIMER_CLK_SRC            34
+#define CSI1PHYTIMER_CLK_SRC            35
+#define CSI2PHYTIMER_CLK_SRC            36
+#define CPP_CLK_SRC                     37
+#define BYTE0_CLK_SRC                   38
+#define BYTE1_CLK_SRC                   39
+#define EDPAUX_CLK_SRC                  40
+#define EDPLINK_CLK_SRC                 41
+#define ESC0_CLK_SRC                    42
+#define ESC1_CLK_SRC                    43
+#define HDMI_CLK_SRC                    44
+#define VSYNC_CLK_SRC                   45
+#define RBCPR_CLK_SRC                   46
+#define RBBMTIMER_CLK_SRC               47
+#define MAPLE_CLK_SRC                   48
+#define VDP_CLK_SRC                     49
+#define VPU_BUS_CLK_SRC                 50
+#define MMSS_CXO_CLK                    51
+#define MMSS_SLEEPCLK_CLK               52
+#define AVSYNC_AHB_CLK                  53
+#define AVSYNC_EDPPIXEL_CLK             54
+#define AVSYNC_EXTPCLK_CLK              55
+#define AVSYNC_PCLK0_CLK                56
+#define AVSYNC_PCLK1_CLK                57
+#define AVSYNC_VP_CLK                   58
+#define CAMSS_AHB_CLK                   59
+#define CAMSS_CCI_CCI_AHB_CLK           60
+#define CAMSS_CCI_CCI_CLK               61
+#define CAMSS_CSI0_AHB_CLK              62
+#define CAMSS_CSI0_CLK                  63
+#define CAMSS_CSI0PHY_CLK               64
+#define CAMSS_CSI0PIX_CLK               65
+#define CAMSS_CSI0RDI_CLK               66
+#define CAMSS_CSI1_AHB_CLK              67
+#define CAMSS_CSI1_CLK                  68
+#define CAMSS_CSI1PHY_CLK               69
+#define CAMSS_CSI1PIX_CLK               70
+#define CAMSS_CSI1RDI_CLK               71
+#define CAMSS_CSI2_AHB_CLK              72
+#define CAMSS_CSI2_CLK                  73
+#define CAMSS_CSI2PHY_CLK               74
+#define CAMSS_CSI2PIX_CLK               75
+#define CAMSS_CSI2RDI_CLK               76
+#define CAMSS_CSI3_AHB_CLK              77
+#define CAMSS_CSI3_CLK                  78
+#define CAMSS_CSI3PHY_CLK               79
+#define CAMSS_CSI3PIX_CLK               80
+#define CAMSS_CSI3RDI_CLK               81
+#define CAMSS_CSI_VFE0_CLK              82
+#define CAMSS_CSI_VFE1_CLK              83
+#define CAMSS_GP0_CLK                   84
+#define CAMSS_GP1_CLK                   85
+#define CAMSS_ISPIF_AHB_CLK             86
+#define CAMSS_JPEG_JPEG0_CLK            87
+#define CAMSS_JPEG_JPEG1_CLK            88
+#define CAMSS_JPEG_JPEG2_CLK            89
+#define CAMSS_JPEG_JPEG_AHB_CLK         90
+#define CAMSS_JPEG_JPEG_AXI_CLK         91
+#define CAMSS_MCLK0_CLK                 92
+#define CAMSS_MCLK1_CLK                 93
+#define CAMSS_MCLK2_CLK                 94
+#define CAMSS_MCLK3_CLK                 95
+#define CAMSS_MICRO_AHB_CLK             96
+#define CAMSS_PHY0_CSI0PHYTIMER_CLK     97
+#define CAMSS_PHY1_CSI1PHYTIMER_CLK     98
+#define CAMSS_PHY2_CSI2PHYTIMER_CLK     99
+#define CAMSS_TOP_AHB_CLK               100
+#define CAMSS_VFE_CPP_AHB_CLK           101
+#define CAMSS_VFE_CPP_CLK               102
+#define CAMSS_VFE_VFE0_CLK              103
+#define CAMSS_VFE_VFE1_CLK              104
+#define CAMSS_VFE_VFE_AHB_CLK           105
+#define CAMSS_VFE_VFE_AXI_CLK           106
+#define MDSS_AHB_CLK                    107
+#define MDSS_AXI_CLK                    108
+#define MDSS_BYTE0_CLK                  109
+#define MDSS_BYTE1_CLK                  110
+#define MDSS_EDPAUX_CLK                 111
+#define MDSS_EDPLINK_CLK                112
+#define MDSS_EDPPIXEL_CLK               113
+#define MDSS_ESC0_CLK                   114
+#define MDSS_ESC1_CLK                   115
+#define MDSS_EXTPCLK_CLK                116
+#define MDSS_HDMI_AHB_CLK               117
+#define MDSS_HDMI_CLK                   118
+#define MDSS_MDP_CLK                    119
+#define MDSS_MDP_LUT_CLK                120
+#define MDSS_PCLK0_CLK                  121
+#define MDSS_PCLK1_CLK                  122
+#define MDSS_VSYNC_CLK                  123
+#define MMSS_RBCPR_AHB_CLK              124
+#define MMSS_RBCPR_CLK                  125
+#define MMSS_SPDM_AHB_CLK               126
+#define MMSS_SPDM_AXI_CLK               127
+#define MMSS_SPDM_CSI0_CLK              128
+#define MMSS_SPDM_GFX3D_CLK             129
+#define MMSS_SPDM_JPEG0_CLK             130
+#define MMSS_SPDM_JPEG1_CLK             131
+#define MMSS_SPDM_JPEG2_CLK             132
+#define MMSS_SPDM_MDP_CLK               133
+#define MMSS_SPDM_PCLK0_CLK             134
+#define MMSS_SPDM_PCLK1_CLK             135
+#define MMSS_SPDM_VCODEC0_CLK           136
+#define MMSS_SPDM_VFE0_CLK              137
+#define MMSS_SPDM_VFE1_CLK              138
+#define MMSS_SPDM_RM_AXI_CLK            139
+#define MMSS_SPDM_RM_OCMEMNOC_CLK       140
+#define MMSS_MISC_AHB_CLK               141
+#define MMSS_MMSSNOC_AHB_CLK            142
+#define MMSS_MMSSNOC_BTO_AHB_CLK        143
+#define MMSS_MMSSNOC_AXI_CLK            144
+#define MMSS_S0_AXI_CLK                 145
+#define OCMEMCX_AHB_CLK                 146
+#define OCMEMCX_OCMEMNOC_CLK            147
+#define OXILI_OCMEMGX_CLK               148
+#define OXILI_GFX3D_CLK                 149
+#define OXILI_RBBMTIMER_CLK             150
+#define OXILICX_AHB_CLK                 151
+#define VENUS0_AHB_CLK                  152
+#define VENUS0_AXI_CLK                  153
+#define VENUS0_CORE0_VCODEC_CLK         154
+#define VENUS0_CORE1_VCODEC_CLK         155
+#define VENUS0_OCMEMNOC_CLK             156
+#define VENUS0_VCODEC0_CLK              157
+#define VPU_AHB_CLK                     158
+#define VPU_AXI_CLK                     159
+#define VPU_BUS_CLK                     160
+#define VPU_CXO_CLK                     161
+#define VPU_MAPLE_CLK                   162
+#define VPU_SLEEP_CLK                   163
+#define VPU_VDP_CLK                     164
+#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
index 5868ef14a777..85041b28f97f 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msm8960.h
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
@@ -133,5 +133,13 @@
 #define CSIPHY0_TIMER_CLK                               116
 #define PLL1                                            117
 #define PLL2                                            118
+#define RGB_TV_CLK                                      119
+#define NPL_TV_CLK                                      120
+#define VCAP_AHB_CLK                                    121
+#define VCAP_AXI_CLK                                    122
+#define VCAP_SRC                                        123
+#define VCAP_CLK                                        124
+#define VCAP_NPL_CLK                                    125
+#define PLL15                                           126
 #endif
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 1118f7a4bca6..f929a79e6998 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -59,6 +59,7 @@
 #define R8A7790_CLK_SDHI0               14
 #define R8A7790_CLK_MMCIF0              15
 #define R8A7790_CLK_IIC0                18
+#define R8A7790_CLK_PCIEC               19
 #define R8A7790_CLK_IIC1                23
 #define R8A7790_CLK_SSUSB               28
 #define R8A7790_CLK_CMT1                29
@@ -107,4 +108,30 @@
 #define R8A7790_CLK_I2C1                30
 #define R8A7790_CLK_I2C0                31
+/* MSTP10 */
+#define R8A7790_CLK_SSI_ALL             5
+#define R8A7790_CLK_SSI9                6
+#define R8A7790_CLK_SSI8                7
+#define R8A7790_CLK_SSI7                8
+#define R8A7790_CLK_SSI6                9
+#define R8A7790_CLK_SSI5                10
+#define R8A7790_CLK_SSI4                11
+#define R8A7790_CLK_SSI3                12
+#define R8A7790_CLK_SSI2                13
+#define R8A7790_CLK_SSI1                14
+#define R8A7790_CLK_SSI0                15
+#define R8A7790_CLK_SCU_ALL             17
+#define R8A7790_CLK_SCU_DVC1            18
+#define R8A7790_CLK_SCU_DVC0            19
+#define R8A7790_CLK_SCU_SRC9            22
+#define R8A7790_CLK_SCU_SRC8            23
+#define R8A7790_CLK_SCU_SRC7            24
+#define R8A7790_CLK_SCU_SRC6            25
+#define R8A7790_CLK_SCU_SRC5            26
+#define R8A7790_CLK_SCU_SRC4            27
+#define R8A7790_CLK_SCU_SRC3            28
+#define R8A7790_CLK_SCU_SRC2            29
+#define R8A7790_CLK_SCU_SRC1            30
+#define R8A7790_CLK_SCU_SRC0            31
 #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index b050d18437ce..f0d4d1049162 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -53,6 +53,7 @@
 #define R8A7791_CLK_SDHI0               14
 #define R8A7791_CLK_MMCIF0              15
 #define R8A7791_CLK_IIC0                18
+#define R8A7791_CLK_PCIEC               19
 #define R8A7791_CLK_IIC1                23
 #define R8A7791_CLK_SSUSB               28
 #define R8A7791_CLK_CMT1                29
@@ -107,6 +108,32 @@
 #define R8A7791_CLK_I2C1                30
 #define R8A7791_CLK_I2C0                31
+/* MSTP10 */
+#define R8A7791_CLK_SSI_ALL             5
+#define R8A7791_CLK_SSI9                6
+#define R8A7791_CLK_SSI8                7
+#define R8A7791_CLK_SSI7                8
+#define R8A7791_CLK_SSI6                9
+#define R8A7791_CLK_SSI5                10
+#define R8A7791_CLK_SSI4                11
+#define R8A7791_CLK_SSI3                12
+#define R8A7791_CLK_SSI2                13
+#define R8A7791_CLK_SSI1                14
+#define R8A7791_CLK_SSI0                15
+#define R8A7791_CLK_SCU_ALL             17
+#define R8A7791_CLK_SCU_DVC1            18
+#define R8A7791_CLK_SCU_DVC0            19
+#define R8A7791_CLK_SCU_SRC9            22
+#define R8A7791_CLK_SCU_SRC8            23
+#define R8A7791_CLK_SCU_SRC7            24
+#define R8A7791_CLK_SCU_SRC6            25
+#define R8A7791_CLK_SCU_SRC5            26
+#define R8A7791_CLK_SCU_SRC4            27
+#define R8A7791_CLK_SCU_SRC3            28
+#define R8A7791_CLK_SCU_SRC2            29
+#define R8A7791_CLK_SCU_SRC1            30
+#define R8A7791_CLK_SCU_SRC0            31
 /* MSTP11 */
 #define R8A7791_CLK_SCIFA3              6
 #define R8A7791_CLK_SCIFA4              7
diff --git a/include/dt-bindings/clock/rk3066a-cru.h b/include/dt-bindings/clock/rk3066a-cru.h
new file mode 100644
index 000000000000..bc1ed1dbd855
--- /dev/null
+++ b/include/dt-bindings/clock/rk3066a-cru.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <dt-bindings/clock/rk3188-cru-common.h>
+/* soft-reset indices */
+#define SRST_SRST1              0
+#define SRST_SRST2              1
+#define SRST_L2MEM              18
+#define SRST_I2S0               23
+#define SRST_I2S1               24
+#define SRST_I2S2               25
+#define SRST_TIMER2             29
+#define SRST_GPIO4              36
+#define SRST_GPIO6              38
+#define SRST_TSADC              92
+#define SRST_HDMI               96
+#define SRST_HDMI_APB           97
+#define SRST_CIF1               111
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
new file mode 100644
index 000000000000..750ee60e75fb
--- /dev/null
+++ b/include/dt-bindings/clock/rk3188-cru-common.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/* core clocks from */
+#define PLL_APLL                1
+#define PLL_DPLL                2
+#define PLL_CPLL                3
+#define PLL_GPLL                4
+#define CORE_PERI               5
+#define CORE_L2C                6
+/* sclk gates (special clocks) */
+#define SCLK_UART0              64
+#define SCLK_UART1              65
+#define SCLK_UART2              66
+#define SCLK_UART3              67
+#define SCLK_MAC                68
+#define SCLK_SPI0               69
+#define SCLK_SPI1               70
+#define SCLK_SARADC             71
+#define SCLK_SDMMC              72
+#define SCLK_SDIO               73
+#define SCLK_EMMC               74
+#define SCLK_I2S0               75
+#define SCLK_I2S1               76
+#define SCLK_I2S2               77
+#define SCLK_SPDIF              78
+#define SCLK_CIF0               79
+#define SCLK_CIF1               80
+#define SCLK_OTGPHY0            81
+#define SCLK_OTGPHY1            82
+#define SCLK_HSADC              83
+#define SCLK_TIMER0             84
+#define SCLK_TIMER1             85
+#define SCLK_TIMER2             86
+#define SCLK_TIMER3             87
+#define SCLK_TIMER4             88
+#define SCLK_TIMER5             89
+#define SCLK_TIMER6             90
+#define SCLK_JTAG               91
+#define SCLK_SMC                92
+#define DCLK_LCDC0              190
+#define DCLK_LCDC1              191
+/* aclk gates */
+#define ACLK_DMA1               192
+#define ACLK_DMA2               193
+#define ACLK_GPS                194
+#define ACLK_LCDC0              195
+#define ACLK_LCDC1              196
+#define ACLK_GPU                197
+#define ACLK_SMC                198
+#define ACLK_CIF                199
+#define ACLK_IPP                200
+#define ACLK_RGA                201
+#define ACLK_CIF0               202
+/* pclk gates */
+#define PCLK_GRF                320
+#define PCLK_PMU                321
+#define PCLK_TIMER0             322
+#define PCLK_TIMER1             323
+#define PCLK_TIMER2             324
+#define PCLK_TIMER3             325
+#define PCLK_PWM01              326
+#define PCLK_PWM23              327
+#define PCLK_SPI0               328
+#define PCLK_SPI1               329
+#define PCLK_SARADC             330
+#define PCLK_WDT                331
+#define PCLK_UART0              332
+#define PCLK_UART1              333
+#define PCLK_UART2              334
+#define PCLK_UART3              335
+#define PCLK_I2C0               336
+#define PCLK_I2C1               337
+#define PCLK_I2C2               338
+#define PCLK_I2C3               339
+#define PCLK_I2C4               340
+#define PCLK_GPIO0              341
+#define PCLK_GPIO1              342
+#define PCLK_GPIO2              343
+#define PCLK_GPIO3              344
+#define PCLK_GPIO4              345
+#define PCLK_GPIO6              346
+#define PCLK_EFUSE              347
+#define PCLK_TZPC               348
+#define PCLK_TSADC              349
+/* hclk gates */
+#define HCLK_SDMMC              448
+#define HCLK_SDIO               449
+#define HCLK_EMMC               450
+#define HCLK_OTG0               451
+#define HCLK_EMAC               452
+#define HCLK_SPDIF              453
+#define HCLK_I2S0               454
+#define HCLK_I2S1               455
+#define HCLK_I2S2               456
+#define HCLK_OTG1               457
+#define HCLK_HSIC               458
+#define HCLK_HSADC              459
+#define HCLK_PIDF               460
+#define HCLK_LCDC0              461
+#define HCLK_LCDC1              462
+#define HCLK_ROM                463
+#define HCLK_CIF0               464
+#define HCLK_IPP                465
+#define HCLK_RGA                466
+#define HCLK_NANDC0             467
+#define CLK_NR_CLKS             (HCLK_NANDC0 + 1)
+/* soft-reset indices */
+#define SRST_MCORE              2
+#define SRST_CORE0              3
+#define SRST_CORE1              4
+#define SRST_MCORE_DBG          7
+#define SRST_CORE0_DBG          8
+#define SRST_CORE1_DBG          9
+#define SRST_CORE0_WDT          12
+#define SRST_CORE1_WDT          13
+#define SRST_STRC_SYS           14
+#define SRST_L2C                15
+#define SRST_CPU_AHB            17
+#define SRST_AHB2APB            19
+#define SRST_DMA1               20
+#define SRST_INTMEM             21
+#define SRST_ROM                22
+#define SRST_SPDIF              26
+#define SRST_TIMER0             27
+#define SRST_TIMER1             28
+#define SRST_EFUSE              30
+#define SRST_GPIO0              32
+#define SRST_GPIO1              33
+#define SRST_GPIO2              34
+#define SRST_GPIO3              35
+#define SRST_UART0              39
+#define SRST_UART1              40
+#define SRST_UART2              41
+#define SRST_UART3              42
+#define SRST_I2C0               43
+#define SRST_I2C1               44
+#define SRST_I2C2               45
+#define SRST_I2C3               46
+#define SRST_I2C4               47
+#define SRST_PWM0               48
+#define SRST_PWM1               49
+#define SRST_DAP_PO             50
+#define SRST_DAP                51
+#define SRST_DAP_SYS            52
+#define SRST_TPIU_ATB           53
+#define SRST_PMU_APB            54
+#define SRST_GRF                55
+#define SRST_PMU                56
+#define SRST_PERI_AXI           57
+#define SRST_PERI_AHB           58
+#define SRST_PERI_APB           59
+#define SRST_PERI_NIU           60
+#define SRST_CPU_PERI           61
+#define SRST_EMEM_PERI          62
+#define SRST_USB_PERI           63
+#define SRST_DMA2               64
+#define SRST_SMC                65
+#define SRST_MAC                66
+#define SRST_NANC0              68
+#define SRST_USBOTG0            69
+#define SRST_USBPHY0            70
+#define SRST_OTGC0              71
+#define SRST_USBOTG1            72
+#define SRST_USBPHY1            73
+#define SRST_OTGC1              74
+#define SRST_HSADC              76
+#define SRST_PIDFILTER          77
+#define SRST_DDR_MSCH           79
+#define SRST_TZPC               80
+#define SRST_SDMMC              81
+#define SRST_SDIO               82
+#define SRST_EMMC               83
+#define SRST_SPI0               84
+#define SRST_SPI1               85
+#define SRST_WDT                86
+#define SRST_SARADC             87
+#define SRST_DDRPHY             88
+#define SRST_DDRPHY_APB         89
+#define SRST_DDRCTL             90
+#define SRST_DDRCTL_APB         91
+#define SRST_DDRPUB             93
+#define SRST_VIO0_AXI           98
+#define SRST_VIO0_AHB           99
+#define SRST_LCDC0_AXI          100
+#define SRST_LCDC0_AHB          101
+#define SRST_LCDC0_DCLK         102
+#define SRST_LCDC1_AXI          103
+#define SRST_LCDC1_AHB          104
+#define SRST_LCDC1_DCLK         105
+#define SRST_IPP_AXI            106
+#define SRST_IPP_AHB            107
+#define SRST_RGA_AXI            108
+#define SRST_RGA_AHB            109
+#define SRST_CIF0               110
+#define SRST_VCODEC_AXI         112
+#define SRST_VCODEC_AHB         113
+#define SRST_VIO1_AXI           114
+#define SRST_VCODEC_CPU         115
+#define SRST_VCODEC_NIU         116
+#define SRST_GPU                120
+#define SRST_GPU_NIU            122
+#define SRST_TFUN_ATB           125
+#define SRST_TFUN_APB           126
+#define SRST_CTI4_APB           127
+#define SRST_TPIU_APB           128
+#define SRST_TRACE              129
+#define SRST_CORE_DBG           130
+#define SRST_DBG_APB            131
+#define SRST_CTI0               132
+#define SRST_CTI0_APB           133
+#define SRST_CTI1               134
+#define SRST_CTI1_APB           135
+#define SRST_PTM_CORE0          136
+#define SRST_PTM_CORE1          137
+#define SRST_PTM0               138
+#define SRST_PTM0_ATB           139
+#define SRST_PTM1               140
+#define SRST_PTM1_ATB           141
+#define SRST_CTM                142
+#define SRST_TS                 143
diff --git a/include/dt-bindings/clock/rk3188-cru.h b/include/dt-bindings/clock/rk3188-cru.h
new file mode 100644
index 000000000000..9fac8edd3f9d
--- /dev/null
+++ b/include/dt-bindings/clock/rk3188-cru.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <dt-bindings/clock/rk3188-cru-common.h>
+/* soft-reset indices */
+#define SRST_PTM_CORE2          0
+#define SRST_PTM_CORE3          1
+#define SRST_CORE2              5
+#define SRST_CORE3              6
+#define SRST_CORE2_DBG          10
+#define SRST_CORE3_DBG          11
+#define SRST_TIMER2             16
+#define SRST_TIMER4             23
+#define SRST_I2S0               24
+#define SRST_TIMER5             25
+#define SRST_TIMER3             29
+#define SRST_TIMER6             31
+#define SRST_PTM3               36
+#define SRST_PTM3_ATB           37
+#define SRST_GPS                67
+#define SRST_HSICPHY            75
+#define SRST_TIMER              78
+#define SRST_PTM2               92
+#define SRST_CORE2_WDT          94
+#define SRST_CORE3_WDT          95
+#define SRST_PTM2_ATB           111
+#define SRST_HSIC               117
+#define SRST_CTI2               118
+#define SRST_CTI2_APB           119
+#define SRST_GPU_BRIDGE         121
+#define SRST_CTI3               123
+#define SRST_CTI3_APB           124
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
new file mode 100644
index 000000000000..ebcb460ea4ad
--- /dev/null
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/* core clocks */
+#define PLL_APLL                1
+#define PLL_DPLL                2
+#define PLL_CPLL                3
+#define PLL_GPLL                4
+#define PLL_NPLL                5
+/* sclk gates (special clocks) */
+#define SCLK_GPU                64
+#define SCLK_SPI0               65
+#define SCLK_SPI1               66
+#define SCLK_SPI2               67
+#define SCLK_SDMMC              68
+#define SCLK_SDIO0              69
+#define SCLK_SDIO1              70
+#define SCLK_EMMC               71
+#define SCLK_TSADC              72
+#define SCLK_SARADC             73
+#define SCLK_PS2C               74
+#define SCLK_NANDC0             75
+#define SCLK_NANDC1             76
+#define SCLK_UART0              77
+#define SCLK_UART1              78
+#define SCLK_UART2              79
+#define SCLK_UART3              80
+#define SCLK_UART4              81
+#define SCLK_I2S0               82
+#define SCLK_SPDIF              83
+#define SCLK_SPDIF8CH           84
+#define SCLK_TIMER0             85
+#define SCLK_TIMER1             86
+#define SCLK_TIMER2             87
+#define SCLK_TIMER3             88
+#define SCLK_TIMER4             89
+#define SCLK_TIMER5             90
+#define SCLK_TIMER6             91
+#define SCLK_HSADC              92
+#define SCLK_OTGPHY0            93
+#define SCLK_OTGPHY1            94
+#define SCLK_OTGPHY2            95
+#define SCLK_OTG_ADP            96
+#define SCLK_HSICPHY480M        97
+#define SCLK_HSICPHY12M         98
+#define SCLK_MACREF             99
+#define SCLK_LCDC_PWM0          100
+#define SCLK_LCDC_PWM1          101
+#define SCLK_MAC_RX             102
+#define SCLK_MAC_TX             103
+#define DCLK_VOP0               190
+#define DCLK_VOP1               191
+/* aclk gates */
+#define ACLK_GPU                192
+#define ACLK_DMAC1              193
+#define ACLK_DMAC2              194
+#define ACLK_MMU                195
+#define ACLK_GMAC               196
+#define ACLK_VOP0               197
+#define ACLK_VOP1               198
+#define ACLK_CRYPTO             199
+#define ACLK_RGA                200
+/* pclk gates */
+#define PCLK_GPIO0              320
+#define PCLK_GPIO1              321
+#define PCLK_GPIO2              322
+#define PCLK_GPIO3              323
+#define PCLK_GPIO4              324
+#define PCLK_GPIO5              325
+#define PCLK_GPIO6              326
+#define PCLK_GPIO7              327
+#define PCLK_GPIO8              328
+#define PCLK_GRF                329
+#define PCLK_SGRF               330
+#define PCLK_PMU                331
+#define PCLK_I2C0               332
+#define PCLK_I2C1               333
+#define PCLK_I2C2               334
+#define PCLK_I2C3               335
+#define PCLK_I2C4               336
+#define PCLK_I2C5               337
+#define PCLK_SPI0               338
+#define PCLK_SPI1               339
+#define PCLK_SPI2               340
+#define PCLK_UART0              341
+#define PCLK_UART1              342
+#define PCLK_UART2              343
+#define PCLK_UART3              344
+#define PCLK_UART4              345
+#define PCLK_TSADC              346
+#define PCLK_SARADC             347
+#define PCLK_SIM                348
+#define PCLK_GMAC               349
+#define PCLK_PWM                350
+#define PCLK_RKPWM              351
+#define PCLK_PS2C               352
+#define PCLK_TIMER              353
+#define PCLK_TZPC               354
+/* hclk gates */
+#define HCLK_GPS                448
+#define HCLK_OTG0               449
+#define HCLK_USBHOST0           450
+#define HCLK_USBHOST1           451
+#define HCLK_HSIC               452
+#define HCLK_NANDC0             453
+#define HCLK_NANDC1             454
+#define HCLK_TSP                455
+#define HCLK_SDMMC              456
+#define HCLK_SDIO0              457
+#define HCLK_SDIO1              458
+#define HCLK_EMMC               459
+#define HCLK_HSADC              460
+#define HCLK_CRYPTO             461
+#define HCLK_I2S0               462
+#define HCLK_SPDIF              463
+#define HCLK_SPDIF8CH           464
+#define HCLK_VOP0               465
+#define HCLK_VOP1               466
+#define HCLK_ROM                467
+#define HCLK_IEP                468
+#define HCLK_ISP                469
+#define HCLK_RGA                470
+#define CLK_NR_CLKS             (HCLK_RGA + 1)
+/* soft-reset indices */
+#define SRST_CORE0              0
+#define SRST_CORE1              1
+#define SRST_CORE2              2
+#define SRST_CORE3              3
+#define SRST_CORE0_PO           4
+#define SRST_CORE1_PO           5
+#define SRST_CORE2_PO           6
+#define SRST_CORE3_PO           7
+#define SRST_PDCORE_STRSYS      8
+#define SRST_PDBUS_STRSYS       9
+#define SRST_L2C                10
+#define SRST_TOPDBG             11
+#define SRST_CORE0_DBG          12
+#define SRST_CORE1_DBG          13
+#define SRST_CORE2_DBG          14
+#define SRST_CORE3_DBG          15
+#define SRST_PDBUG_AHB_ARBITOR  16
+#define SRST_EFUSE256           17
+#define SRST_DMAC1              18
+#define SRST_INTMEM             19
+#define SRST_ROM                20
+#define SRST_SPDIF8CH           21
+#define SRST_TIMER              22
+#define SRST_I2S0               23
+#define SRST_SPDIF              24
+#define SRST_TIMER0             25
+#define SRST_TIMER1             26
+#define SRST_TIMER2             27
+#define SRST_TIMER3             28
+#define SRST_TIMER4             29
+#define SRST_TIMER5             30
+#define SRST_EFUSE              31
+#define SRST_GPIO0              32
+#define SRST_GPIO1              33
+#define SRST_GPIO2              34
+#define SRST_GPIO3              35
+#define SRST_GPIO4              36
+#define SRST_GPIO5              37
+#define SRST_GPIO6              38
+#define SRST_GPIO7              39
+#define SRST_GPIO8              40
+#define SRST_I2C0               42
+#define SRST_I2C1               43
+#define SRST_I2C2               44
+#define SRST_I2C3               45
+#define SRST_I2C4               46
+#define SRST_I2C5               47
+#define SRST_DWPWM              48
+#define SRST_MMC_PERI           49
+#define SRST_PERIPH_MMU         50
+#define SRST_DAP                51
+#define SRST_DAP_SYS            52
+#define SRST_TPIU               53
+#define SRST_PMU_APB            54
+#define SRST_GRF                55
+#define SRST_PMU                56
+#define SRST_PERIPH_AXI         57
+#define SRST_PERIPH_AHB         58
+#define SRST_PERIPH_APB         59
+#define SRST_PERIPH_NIU         60
+#define SRST_PDPERI_AHB_ARBI    61
+#define SRST_EMEM               62
+#define SRST_USB_PERI           63
+#define SRST_DMAC2              64
+#define SRST_MAC                66
+#define SRST_GPS                67
+#define SRST_RKPWM              69
+#define SRST_CCP                71
+#define SRST_USBHOST0           72
+#define SRST_HSIC               73
+#define SRST_HSIC_AUX           74
+#define SRST_HSIC_PHY           75
+#define SRST_HSADC              76
+#define SRST_NANDC0             77
+#define SRST_NANDC1             78
+#define SRST_TZPC               80
+#define SRST_SPI0               83
+#define SRST_SPI1               84
+#define SRST_SPI2               85
+#define SRST_SARADC             87
+#define SRST_PDALIVE_NIU        88
+#define SRST_PDPMU_INTMEM       89
+#define SRST_PDPMU_NIU          90
+#define SRST_SGRF               91
+#define SRST_VIO_ARBI           96
+#define SRST_RGA_NIU            97
+#define SRST_VIO0_NIU_AXI       98
+#define SRST_VIO_NIU_AHB        99
+#define SRST_LCDC0_AXI          100
+#define SRST_LCDC0_AHB          101
+#define SRST_LCDC0_DCLK         102
+#define SRST_VIO1_NIU_AXI       103
+#define SRST_VIP                104
+#define SRST_RGA_CORE           105
+#define SRST_IEP_AXI            106
+#define SRST_IEP_AHB            107
+#define SRST_RGA_AXI            108
+#define SRST_RGA_AHB            109
+#define SRST_ISP                110
+#define SRST_EDP                111
+#define SRST_VCODEC_AXI         112
+#define SRST_VCODEC_AHB         113
+#define SRST_VIO_H2P            114
+#define SRST_MIPIDSI0           115
+#define SRST_MIPIDSI1           116
+#define SRST_MIPICSI            117
+#define SRST_LVDS_PHY           118
+#define SRST_LVDS_CON           119
+#define SRST_GPU                120
+#define SRST_HDMI               121
+#define SRST_CORE_PVTM          124
+#define SRST_GPU_PVTM           125
+#define SRST_MMC0               128
+#define SRST_SDIO0              129
+#define SRST_SDIO1              130
+#define SRST_EMMC               131
+#define SRST_USBOTG_AHB         132
+#define SRST_USBOTG_PHY         133
+#define SRST_USBOTG_CON         134
+#define SRST_USBHOST0_AHB       135
+#define SRST_USBHOST0_PHY       136
+#define SRST_USBHOST0_CON       137
+#define SRST_USBHOST1_AHB       138
+#define SRST_USBHOST1_PHY       139
+#define SRST_USBHOST1_CON       140
+#define SRST_USB_ADP            141
+#define SRST_ACC_EFUSE          142
diff --git a/include/dt-bindings/clock/s5pv210-audss.h b/include/dt-bindings/clock/s5pv210-audss.h
new file mode 100644
index 000000000000..fe57406e24de
--- /dev/null
+++ b/include/dt-bindings/clock/s5pv210-audss.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2014 Tomasz Figa <tomasz.figa@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and s5pv210 audss driver.
+ */
+#ifndef _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
+#define _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
+#define CLK_MOUT_AUDSS          0
+#define CLK_MOUT_I2S_A          1
+#define CLK_DOUT_AUD_BUS        2
+#define CLK_DOUT_I2S_A          3
+#define CLK_I2S                 4
+#define CLK_HCLK_I2S            5
+#define CLK_HCLK_UART           6
+#define CLK_HCLK_HWA            7
+#define CLK_HCLK_DMA            8
+#define CLK_HCLK_BUF            9
+#define CLK_HCLK_RP             10
+#define AUDSS_MAX_CLKS          11
+#endif
diff --git a/include/dt-bindings/clock/s5pv210.h b/include/dt-bindings/clock/s5pv210.h
new file mode 100644
index 000000000000..e88986b7c677
--- /dev/null
+++ b/include/dt-bindings/clock/s5pv210.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung S5PV210 clock controller.
+ */
+#ifndef _DT_BINDINGS_CLOCK_S5PV210_H
+#define _DT_BINDINGS_CLOCK_S5PV210_H
+/* Core clocks. */
+#define FIN_PLL                 1
+#define FOUT_APLL               2
+#define FOUT_MPLL               3
+#define FOUT_EPLL               4
+#define FOUT_VPLL               5
+/* Muxes. */
+#define MOUT_FLASH              6
+#define MOUT_PSYS               7
+#define MOUT_DSYS               8
+#define MOUT_MSYS               9
+#define MOUT_VPLL               10
+#define MOUT_EPLL               11
+#define MOUT_MPLL               12
+#define MOUT_APLL               13
+#define MOUT_VPLLSRC            14
+#define MOUT_CSIS               15
+#define MOUT_FIMD               16
+#define MOUT_CAM1               17
+#define MOUT_CAM0               18
+#define MOUT_DAC                19
+#define MOUT_MIXER              20
+#define MOUT_HDMI               21
+#define MOUT_G2D                22
+#define MOUT_MFC                23
+#define MOUT_G3D                24
+#define MOUT_FIMC2              25
+#define MOUT_FIMC1              26
+#define MOUT_FIMC0              27
+#define MOUT_UART3              28
+#define MOUT_UART2              29
+#define MOUT_UART1              30
+#define MOUT_UART0              31
+#define MOUT_MMC3               32
+#define MOUT_MMC2               33
+#define MOUT_MMC1               34
+#define MOUT_MMC0               35
+#define MOUT_PWM                36
+#define MOUT_SPI0               37
+#define MOUT_SPI1               38
+#define MOUT_DMC0               39
+#define MOUT_PWI                40
+#define MOUT_HPM                41
+#define MOUT_SPDIF              42
+#define MOUT_AUDIO2             43
+#define MOUT_AUDIO1             44
+#define MOUT_AUDIO0             45
+/* Dividers. */
+#define DOUT_PCLKP              46
+#define DOUT_HCLKP              47
+#define DOUT_PCLKD              48
+#define DOUT_HCLKD              49
+#define DOUT_PCLKM              50
+#define DOUT_HCLKM              51
+#define DOUT_A2M                52
+#define DOUT_APLL               53
+#define DOUT_CSIS               54
+#define DOUT_FIMD               55
+#define DOUT_CAM1               56
+#define DOUT_CAM0               57
+#define DOUT_TBLK               58
+#define DOUT_G2D                59
+#define DOUT_MFC                60
+#define DOUT_G3D                61
+#define DOUT_FIMC2              62
+#define DOUT_FIMC1              63
+#define DOUT_FIMC0              64
+#define DOUT_UART3              65
+#define DOUT_UART2              66
+#define DOUT_UART1              67
+#define DOUT_UART0              68
+#define DOUT_MMC3               69
+#define DOUT_MMC2               70
+#define DOUT_MMC1               71
+#define DOUT_MMC0               72
+#define DOUT_PWM                73
+#define DOUT_SPI1               74
+#define DOUT_SPI0               75
+#define DOUT_DMC0               76
+#define DOUT_PWI                77
+#define DOUT_HPM                78
+#define DOUT_COPY               79
+#define DOUT_FLASH              80
+#define DOUT_AUDIO2             81
+#define DOUT_AUDIO1             82
+#define DOUT_AUDIO0             83
+#define DOUT_DPM                84
+#define DOUT_DVSEM              85
+/* Gates */
+#define SCLK_FIMC               86
+#define CLK_CSIS                87
+#define CLK_ROTATOR             88
+#define CLK_FIMC2               89
+#define CLK_FIMC1               90
+#define CLK_FIMC0               91
+#define CLK_MFC                 92
+#define CLK_G2D                 93
+#define CLK_G3D                 94
+#define CLK_IMEM                95
+#define CLK_PDMA1               96
+#define CLK_PDMA0               97
+#define CLK_MDMA                98
+#define CLK_DMC1                99
+#define CLK_DMC0                100
+#define CLK_NFCON               101
+#define CLK_SROMC               102
+#define CLK_CFCON               103
+#define CLK_NANDXL              104
+#define CLK_USB_HOST            105
+#define CLK_USB_OTG             106
+#define CLK_HDMI                107
+#define CLK_TVENC               108
+#define CLK_MIXER               109
+#define CLK_VP                  110
+#define CLK_DSIM                111
+#define CLK_FIMD                112
+#define CLK_TZIC3               113
+#define CLK_TZIC2               114
+#define CLK_TZIC1               115
+#define CLK_TZIC0               116
+#define CLK_VIC3                117
+#define CLK_VIC2                118
+#define CLK_VIC1                119
+#define CLK_VIC0                120
+#define CLK_TSI                 121
+#define CLK_HSMMC3              122
+#define CLK_HSMMC2              123
+#define CLK_HSMMC1              124
+#define CLK_HSMMC0              125
+#define CLK_JTAG                126
+#define CLK_MODEMIF             127
+#define CLK_CORESIGHT           128
+#define CLK_SDM                 129
+#define CLK_SECSS               130
+#define CLK_PCM2                131
+#define CLK_PCM1                132
+#define CLK_PCM0                133
+#define CLK_SYSCON              134
+#define CLK_GPIO                135
+#define CLK_TSADC               136
+#define CLK_PWM                 137
+#define CLK_WDT                 138
+#define CLK_KEYIF               139
+#define CLK_UART3               140
+#define CLK_UART2               141
+#define CLK_UART1               142
+#define CLK_UART0               143
+#define CLK_SYSTIMER            144
+#define CLK_RTC                 145
+#define CLK_SPI1                146
+#define CLK_SPI0                147
+#define CLK_I2C_HDMI_PHY        148
+#define CLK_I2C1                149
+#define CLK_I2C2                150
+#define CLK_I2C0                151
+#define CLK_I2S1                152
+#define CLK_I2S2                153
+#define CLK_I2S0                154
+#define CLK_AC97                155
+#define CLK_SPDIF               156
+#define CLK_TZPC3               157
+#define CLK_TZPC2               158
+#define CLK_TZPC1               159
+#define CLK_TZPC0               160
+#define CLK_SECKEY              161
+#define CLK_IEM_APC             162
+#define CLK_IEM_IEC             163
+#define CLK_CHIPID              164
+#define CLK_JPEG                163
+/* Special clocks*/
+#define SCLK_PWI                164
+#define SCLK_SPDIF              165
+#define SCLK_AUDIO2             166
+#define SCLK_AUDIO1             167
+#define SCLK_AUDIO0             168
+#define SCLK_PWM                169
+#define SCLK_SPI1               170
+#define SCLK_SPI0               171
+#define SCLK_UART3              172
+#define SCLK_UART2              173
+#define SCLK_UART1              174
+#define SCLK_UART0              175
+#define SCLK_MMC3               176
+#define SCLK_MMC2               177
+#define SCLK_MMC1               178
+#define SCLK_MMC0               179
+#define SCLK_FINVPLL            180
+#define SCLK_CSIS               181
+#define SCLK_FIMD               182
+#define SCLK_CAM1               183
+#define SCLK_CAM0               184
+#define SCLK_DAC                185
+#define SCLK_MIXER              186
+#define SCLK_HDMI               187
+#define SCLK_FIMC2              188
+#define SCLK_FIMC1              189
+#define SCLK_FIMC0              190
+#define SCLK_HDMI27M            191
+#define SCLK_HDMIPHY            192
+#define SCLK_USBPHY0            193
+#define SCLK_USBPHY1            194
+/* S5P6442-specific clocks */
+#define MOUT_D0SYNC             195
+#define MOUT_D1SYNC             196
+#define DOUT_MIXER              197
+#define CLK_ETB                 198
+#define CLK_ETM                 199
+/* CLKOUT */
+#define FOUT_APLL_CLKOUT        200
+#define FOUT_MPLL_CLKOUT        201
+#define DOUT_APLL_CLKOUT        202
+#define MOUT_CLKSEL             203
+#define DOUT_CLKOUT             204
+#define MOUT_CLKOUT             205
+/* Total number of clocks. */
+#define NR_CLKS                 206
+#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index a91602951d3d..00953d9484cb 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -164,6 +164,8 @@
 #define VF610_CLK_DMAMUX1               151
 #define VF610_CLK_DMAMUX2               152
 #define VF610_CLK_DMAMUX3               153
-#define VF610_CLK_END                   154
+#define VF610_CLK_FLEXCAN0_EN           154
+#define VF610_CLK_FLEXCAN1_EN           155
+#define VF610_CLK_END                   156
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/dt-bindings/dma/nbpfaxi.h b/include/dt-bindings/dma/nbpfaxi.h
new file mode 100644
index 000000000000..c1a5b9e0d6a4
--- /dev/null
+++ b/include/dt-bindings/dma/nbpfaxi.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
+ * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ */
+#ifndef DT_BINDINGS_NBPFAXI_H
+#define DT_BINDINGS_NBPFAXI_H
+/**
+ * Use "#dma-cells = <2>;" with the second integer defining slave DMA flags:
+ */
+#define NBPF_SLAVE_RQ_HIGH      1
+#define NBPF_SLAVE_RQ_LOW       2
+#define NBPF_SLAVE_RQ_LEVEL     4
+#endif
diff --git a/include/dt-bindings/mfd/as3722.h b/include/dt-bindings/mfd/as3722.h
index 0e692562d77b..e66c0898c58e 100644
--- a/include/dt-bindings/mfd/as3722.h
+++ b/include/dt-bindings/mfd/as3722.h
@@ -13,7 +13,7 @@
 /* External control pins */
 #define AS3722_EXT_CONTROL_PIN_ENABLE1 1
 #define AS3722_EXT_CONTROL_PIN_ENABLE2 2
-#define AS3722_EXT_CONTROL_PIN_ENABLE2 3
+#define AS3722_EXT_CONTROL_PIN_ENABLE3 3
 /* Interrupt numbers for AS3722 */
 #define AS3722_IRQ_LID                  0
diff --git a/include/dt-bindings/mfd/palmas.h b/include/dt-bindings/mfd/palmas.h
new file mode 100644
index 000000000000..2c8ac4841385
--- /dev/null
+++ b/include/dt-bindings/mfd/palmas.h
@@ -0,0 +1,18 @@
+/*
+ * This header provides macros for Palmas device bindings.
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ */
+#ifndef __DT_BINDINGS_PALMAS_H__
+#define __DT_BINDINGS_PALMAS_H
+/* External control pins */
+#define PALMAS_EXT_CONTROL_PIN_ENABLE1  1
+#define PALMAS_EXT_CONTROL_PIN_ENABLE2  2
+#define PALMAS_EXT_CONTROL_PIN_NSLEEP   3
+#endif /* __DT_BINDINGS_PALMAS_H */
diff --git a/include/dt-bindings/phy/phy-miphy365x.h b/include/dt-bindings/phy/phy-miphy365x.h
new file mode 100644
index 000000000000..8ef8aba6edd6
--- /dev/null
+++ b/include/dt-bindings/phy/phy-miphy365x.h
@@ -0,0 +1,14 @@
+/*
+ * This header provides constants for the phy framework
+ * based on the STMicroelectronics MiPHY365x.
+ *
+ * Author: Lee Jones <lee.jones@linaro.org>
+ */
+#ifndef _DT_BINDINGS_PHY_MIPHY
+#define _DT_BINDINGS_PHY_MIPHY
+#define MIPHY_TYPE_SATA         1
+#define MIPHY_TYPE_PCIE         2
+#define MIPHY_TYPE_USB          3
+#endif /* _DT_BINDINGS_PHY_MIPHY */
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
index 002a2855c046..3d33794e4f3e 100644
--- a/include/dt-bindings/pinctrl/dra.h
+++ b/include/dt-bindings/pinctrl/dra.h
@@ -30,7 +30,8 @@
 #define MUX_MODE14      0xe
 #define MUX_MODE15      0xf
-#define PULL_ENA                (1 << 16)
+#define PULL_ENA                (0 << 16)
+#define PULL_DIS                (1 << 16)
 #define PULL_UP                 (1 << 17)
 #define INPUT_EN                (1 << 18)
 #define SLEWCONTROL             (1 << 19)
@@ -38,10 +39,10 @@
 #define WAKEUP_EVENT            (1 << 25)
 /* Active pin states */
-#define PIN_OUTPUT              0
+#define PIN_OUTPUT              (0 | PULL_DIS)
 #define PIN_OUTPUT_PULLUP       (PIN_OUTPUT | PULL_ENA | PULL_UP)
 #define PIN_OUTPUT_PULLDOWN     (PIN_OUTPUT | PULL_ENA)
-#define PIN_INPUT               INPUT_EN
+#define PIN_INPUT               (INPUT_EN | PULL_DIS)
 #define PIN_INPUT_SLEW          (INPUT_EN | SLEWCONTROL)
 #define PIN_INPUT_PULLUP        (PULL_ENA | INPUT_EN | PULL_UP)
 #define PIN_INPUT_PULLDOWN      (PULL_ENA | INPUT_EN)
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h
new file mode 100644
index 000000000000..914d56da9324
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h
@@ -0,0 +1,7 @@
+#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H
+#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1
+#define TEGRA_XUSB_PADCTL_PCIE 0
+#define TEGRA_XUSB_PADCTL_SATA 1
+#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */
diff --git a/include/dt-bindings/reset/qcom,gcc-apq8084.h b/include/dt-bindings/reset/qcom,gcc-apq8084.h
new file mode 100644
index 000000000000..527caaf48e3d
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-apq8084.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H
+#define _DT_BINDINGS_RESET_APQ_GCC_8084_H
+#define GCC_SYSTEM_NOC_BCR              0
+#define GCC_CONFIG_NOC_BCR              1
+#define GCC_PERIPH_NOC_BCR              2
+#define GCC_IMEM_BCR                    3
+#define GCC_MMSS_BCR                    4
+#define GCC_QDSS_BCR                    5
+#define GCC_USB_30_BCR                  6
+#define GCC_USB3_PHY_BCR                7
+#define GCC_USB_HS_HSIC_BCR             8
+#define GCC_USB_HS_BCR                  9
+#define GCC_USB2A_PHY_BCR               10
+#define GCC_USB2B_PHY_BCR               11
+#define GCC_SDCC1_BCR                   12
+#define GCC_SDCC2_BCR                   13
+#define GCC_SDCC3_BCR                   14
+#define GCC_SDCC4_BCR                   15
+#define GCC_BLSP1_BCR                   16
+#define GCC_BLSP1_QUP1_BCR              17
+#define GCC_BLSP1_UART1_BCR             18
+#define GCC_BLSP1_QUP2_BCR              19
+#define GCC_BLSP1_UART2_BCR             20
+#define GCC_BLSP1_QUP3_BCR              21
+#define GCC_BLSP1_UART3_BCR             22
+#define GCC_BLSP1_QUP4_BCR              23
+#define GCC_BLSP1_UART4_BCR             24
+#define GCC_BLSP1_QUP5_BCR              25
+#define GCC_BLSP1_UART5_BCR             26
+#define GCC_BLSP1_QUP6_BCR              27
+#define GCC_BLSP1_UART6_BCR             28
+#define GCC_BLSP2_BCR                   29
+#define GCC_BLSP2_QUP1_BCR              30
+#define GCC_BLSP2_UART1_BCR             31
+#define GCC_BLSP2_QUP2_BCR              32
+#define GCC_BLSP2_UART2_BCR             33
+#define GCC_BLSP2_QUP3_BCR              34
+#define GCC_BLSP2_UART3_BCR             35
+#define GCC_BLSP2_QUP4_BCR              36
+#define GCC_BLSP2_UART4_BCR             37
+#define GCC_BLSP2_QUP5_BCR              38
+#define GCC_BLSP2_UART5_BCR             39
+#define GCC_BLSP2_QUP6_BCR              40
+#define GCC_BLSP2_UART6_BCR             41
+#define GCC_PDM_BCR                     42
+#define GCC_PRNG_BCR                    43
+#define GCC_BAM_DMA_BCR                 44
+#define GCC_TSIF_BCR                    45
+#define GCC_TCSR_BCR                    46
+#define GCC_BOOT_ROM_BCR                47
+#define GCC_MSG_RAM_BCR                 48
+#define GCC_TLMM_BCR                    49
+#define GCC_MPM_BCR                     50
+#define GCC_MPM_AHB_RESET               51
+#define GCC_MPM_NON_AHB_RESET           52
+#define GCC_SEC_CTRL_BCR                53
+#define GCC_SPMI_BCR                    54
+#define GCC_SPDM_BCR                    55
+#define GCC_CE1_BCR                     56
+#define GCC_CE2_BCR                     57
+#define GCC_BIMC_BCR                    58
+#define GCC_SNOC_BUS_TIMEOUT0_BCR       59
+#define GCC_SNOC_BUS_TIMEOUT2_BCR       60
+#define GCC_PNOC_BUS_TIMEOUT0_BCR       61
+#define GCC_PNOC_BUS_TIMEOUT1_BCR       62
+#define GCC_PNOC_BUS_TIMEOUT2_BCR       63
+#define GCC_PNOC_BUS_TIMEOUT3_BCR       64
+#define GCC_PNOC_BUS_TIMEOUT4_BCR       65
+#define GCC_CNOC_BUS_TIMEOUT0_BCR       66
+#define GCC_CNOC_BUS_TIMEOUT1_BCR       67
+#define GCC_CNOC_BUS_TIMEOUT2_BCR       68
+#define GCC_CNOC_BUS_TIMEOUT3_BCR       69
+#define GCC_CNOC_BUS_TIMEOUT4_BCR       70
+#define GCC_CNOC_BUS_TIMEOUT5_BCR       71
+#define GCC_CNOC_BUS_TIMEOUT6_BCR       72
+#define GCC_DEHR_BCR                    73
+#define GCC_RBCPR_BCR                   74
+#define GCC_MSS_RESTART                 75
+#define GCC_LPASS_RESTART               76
+#define GCC_WCSS_RESTART                77
+#define GCC_VENUS_RESTART               78
+#define GCC_COPSS_SMMU_BCR              79
+#define GCC_SPSS_BCR                    80
+#define GCC_PCIE_0_BCR                  81
+#define GCC_PCIE_0_PHY_BCR              82
+#define GCC_PCIE_1_BCR                  83
+#define GCC_PCIE_1_PHY_BCR              84
+#define GCC_USB_30_SEC_BCR              85
+#define GCC_USB3_SEC_PHY_BCR            86
+#define GCC_SATA_BCR                    87
+#define GCC_CE3_BCR                     88
+#define GCC_UFS_BCR                     89
+#define GCC_USB30_PHY_COM_BCR           90
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
new file mode 100644
index 000000000000..0ad5ef930b5d
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_RESET_IPQ_806X_H
+#define _DT_BINDINGS_RESET_IPQ_806X_H
+#define QDSS_STM_RESET                                  0
+#define AFAB_SMPSS_S_RESET                              1
+#define AFAB_SMPSS_M1_RESET                             2
+#define AFAB_SMPSS_M0_RESET                             3
+#define AFAB_EBI1_CH0_RESET                             4
+#define AFAB_EBI1_CH1_RESET                             5
+#define SFAB_ADM0_M0_RESET                              6
+#define SFAB_ADM0_M1_RESET                              7
+#define SFAB_ADM0_M2_RESET                              8
+#define ADM0_C2_RESET                                   9
+#define ADM0_C1_RESET                                   10
+#define ADM0_C0_RESET                                   11
+#define ADM0_PBUS_RESET                                 12
+#define ADM0_RESET                                      13
+#define QDSS_CLKS_SW_RESET                              14
+#define QDSS_POR_RESET                                  15
+#define QDSS_TSCTR_RESET                                16
+#define QDSS_HRESET_RESET                               17
+#define QDSS_AXI_RESET                                  18
+#define QDSS_DBG_RESET                                  19
+#define SFAB_PCIE_M_RESET                               20
+#define SFAB_PCIE_S_RESET                               21
+#define PCIE_EXT_RESET                                  22
+#define PCIE_PHY_RESET                                  23
+#define PCIE_PCI_RESET                                  24
+#define PCIE_POR_RESET                                  25
+#define PCIE_HCLK_RESET                                 26
+#define PCIE_ACLK_RESET                                 27
+#define SFAB_LPASS_RESET                                28
+#define SFAB_AFAB_M_RESET                               29
+#define AFAB_SFAB_M0_RESET                              30
+#define AFAB_SFAB_M1_RESET                              31
+#define SFAB_SATA_S_RESET                               32
+#define SFAB_DFAB_M_RESET                               33
+#define DFAB_SFAB_M_RESET                               34
+#define DFAB_SWAY0_RESET                                35
+#define DFAB_SWAY1_RESET                                36
+#define DFAB_ARB0_RESET                                 37
+#define DFAB_ARB1_RESET                                 38
+#define PPSS_PROC_RESET                                 39
+#define PPSS_RESET                                      40
+#define DMA_BAM_RESET                                   41
+#define SPS_TIC_H_RESET                                 42
+#define SFAB_CFPB_M_RESET                               43
+#define SFAB_CFPB_S_RESET                               44
+#define TSIF_H_RESET                                    45
+#define CE1_H_RESET                                     46
+#define CE1_CORE_RESET                                  47
+#define CE1_SLEEP_RESET                                 48
+#define CE2_H_RESET                                     49
+#define CE2_CORE_RESET                                  50
+#define SFAB_SFPB_M_RESET                               51
+#define SFAB_SFPB_S_RESET                               52
+#define RPM_PROC_RESET                                  53
+#define PMIC_SSBI2_RESET                                54
+#define SDC1_RESET                                      55
+#define SDC2_RESET                                      56
+#define SDC3_RESET                                      57
+#define SDC4_RESET                                      58
+#define USB_HS1_RESET                                   59
+#define USB_HSIC_RESET                                  60
+#define USB_FS1_XCVR_RESET                              61
+#define USB_FS1_RESET                                   62
+#define GSBI1_RESET                                     63
+#define GSBI2_RESET                                     64
+#define GSBI3_RESET                                     65
+#define GSBI4_RESET                                     66
+#define GSBI5_RESET                                     67
+#define GSBI6_RESET                                     68
+#define GSBI7_RESET                                     69
+#define SPDM_RESET                                      70
+#define SEC_CTRL_RESET                                  71
+#define TLMM_H_RESET                                    72
+#define SFAB_SATA_M_RESET                               73
+#define SATA_RESET                                      74
+#define TSSC_RESET                                      75
+#define PDM_RESET                                       76
+#define MPM_H_RESET                                     77
+#define MPM_RESET                                       78
+#define SFAB_SMPSS_S_RESET                              79
+#define PRNG_RESET                                      80
+#define SFAB_CE3_M_RESET                                81
+#define SFAB_CE3_S_RESET                                82
+#define CE3_SLEEP_RESET                                 83
+#define PCIE_1_M_RESET                                  84
+#define PCIE_1_S_RESET                                  85
+#define PCIE_1_EXT_RESET                                86
+#define PCIE_1_PHY_RESET                                87
+#define PCIE_1_PCI_RESET                                88
+#define PCIE_1_POR_RESET                                89
+#define PCIE_1_HCLK_RESET                               90
+#define PCIE_1_ACLK_RESET                               91
+#define PCIE_2_M_RESET                                  92
+#define PCIE_2_S_RESET                                  93
+#define PCIE_2_EXT_RESET                                94
+#define PCIE_2_PHY_RESET                                95
+#define PCIE_2_PCI_RESET                                96
+#define PCIE_2_POR_RESET                                97
+#define PCIE_2_HCLK_RESET                               98
+#define PCIE_2_ACLK_RESET                               99
+#define SFAB_USB30_S_RESET                              100
+#define SFAB_USB30_M_RESET                              101
+#define USB30_0_PORT2_HS_PHY_RESET                      102
+#define USB30_0_MASTER_RESET                            103
+#define USB30_0_SLEEP_RESET                             104
+#define USB30_0_UTMI_PHY_RESET                          105
+#define USB30_0_POWERON_RESET                           106
+#define USB30_0_PHY_RESET                               107
+#define USB30_1_MASTER_RESET                            108
+#define USB30_1_SLEEP_RESET                             109
+#define USB30_1_UTMI_PHY_RESET                          110
+#define USB30_1_POWERON_RESET                           111
+#define USB30_1_PHY_RESET                               112
+#define NSSFB0_RESET                                    113
+#define NSSFB1_RESET                                    114
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8960.h b/include/dt-bindings/reset/qcom,gcc-msm8960.h
index 07edd0e65eed..47c8686955da 100644
--- a/include/dt-bindings/reset/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/reset/qcom,gcc-msm8960.h
@@ -114,5 +114,21 @@
 #define SFAB_SMPSS_S_RESET                              97
 #define PRNG_RESET                                      98
 #define RIVA_RESET                                      99
+#define USB_HS3_RESET                                   100
+#define USB_HS4_RESET                                   101
+#define CE3_RESET                                       102
+#define PCIE_EXT_PCI_RESET                              103
+#define PCIE_PHY_RESET                                  104
+#define PCIE_PCI_RESET                                  105
+#define PCIE_POR_RESET                                  106
+#define PCIE_HCLK_RESET                                 107
+#define PCIE_ACLK_RESET                                 108
+#define CE3_H_RESET                                     109
+#define SFAB_CE3_M_RESET                                110
+#define SFAB_CE3_S_RESET                                111
+#define SATA_RESET                                      112
+#define CE3_SLEEP_RESET                                 113
+#define GSS_SLP_RESET                                   114
+#define GSS_RESET                                       115
 #endif
diff --git a/include/dt-bindings/reset/qcom,mmcc-apq8084.h b/include/dt-bindings/reset/qcom,mmcc-apq8084.h
new file mode 100644
index 000000000000..c1671396531d
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,mmcc-apq8084.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H
+#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H
+#define MMSS_SPDM_RESET                 0
+#define MMSS_SPDM_RM_RESET              1
+#define VENUS0_RESET                    2
+#define VPU_RESET                       3
+#define MDSS_RESET                      4
+#define AVSYNC_RESET                    5
+#define CAMSS_PHY0_RESET                6
+#define CAMSS_PHY1_RESET                7
+#define CAMSS_PHY2_RESET                8
+#define CAMSS_CSI0_RESET                9
+#define CAMSS_CSI0PHY_RESET             10
+#define CAMSS_CSI0RDI_RESET             11
+#define CAMSS_CSI0PIX_RESET             12
+#define CAMSS_CSI1_RESET                13
+#define CAMSS_CSI1PHY_RESET             14
+#define CAMSS_CSI1RDI_RESET             15
+#define CAMSS_CSI1PIX_RESET             16
+#define CAMSS_CSI2_RESET                17
+#define CAMSS_CSI2PHY_RESET             18
+#define CAMSS_CSI2RDI_RESET             19
+#define CAMSS_CSI2PIX_RESET             20
+#define CAMSS_CSI3_RESET                21
+#define CAMSS_CSI3PHY_RESET             22
+#define CAMSS_CSI3RDI_RESET             23
+#define CAMSS_CSI3PIX_RESET             24
+#define CAMSS_ISPIF_RESET               25
+#define CAMSS_CCI_RESET                 26
+#define CAMSS_MCLK0_RESET               27
+#define CAMSS_MCLK1_RESET               28
+#define CAMSS_MCLK2_RESET               29
+#define CAMSS_MCLK3_RESET               30
+#define CAMSS_GP0_RESET                 31
+#define CAMSS_GP1_RESET                 32
+#define CAMSS_TOP_RESET                 33
+#define CAMSS_AHB_RESET                 34
+#define CAMSS_MICRO_RESET               35
+#define CAMSS_JPEG_RESET                36
+#define CAMSS_VFE_RESET                 37
+#define CAMSS_CSI_VFE0_RESET            38
+#define CAMSS_CSI_VFE1_RESET            39
+#define OXILI_RESET                     40
+#define OXILICX_RESET                   41
+#define OCMEMCX_RESET                   42
+#define MMSS_RBCRP_RESET                43
+#define MMSSNOCAHB_RESET                44
+#define MMSSNOCAXI_RESET                45
+#endif
diff --git a/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/include/dt-bindings/reset/qcom,mmcc-msm8960.h
index ba36ec680118..11741113a841 100644
--- a/include/dt-bindings/reset/qcom,mmcc-msm8960.h
+++ b/include/dt-bindings/reset/qcom,mmcc-msm8960.h
@@ -89,5 +89,13 @@
 #define CSI2_RESET                                      72
 #define CSI_RDI1_RESET                                  73
 #define CSI_RDI2_RESET                                  74
+#define GFX3D_AXI_RESET                                 75
+#define VCAP_AXI_RESET                                  76
+#define SMMU_VCAP_AHB_RESET                             77
+#define VCAP_AHB_RESET                                  78
+#define CSI_RDI_RESET                                   79
+#define CSI_PIX_RESET                                   80
+#define VCAP_NPL_RESET                                  81
+#define VCAP_RESET                                      82
 #endif
author	Dmitry Torokhov <dmitry.torokhov@gmail.com>	2014-09-03 19:01:36 -0400
committer	Dmitry Torokhov <dmitry.torokhov@gmail.com>	2014-09-03 19:01:36 -0400
commit	516d5f8b04ce2bcd24f03323fc743ae25b81373d (patch)
tree	ff37e84692dbef5063bbf22672eb8bfad0f25dd8 /include/dt-bindings
parent	6ba694560caeb3531dbedd5b3a37af037ef2a833 (diff)
parent	69e273c0b0a3c337a521d083374c918dc52c666f (diff)