ARM: shmobile: Initial r8a7794 SoC device tree

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
[uli: reduced to minimum, added cmt, enabled scif2, split off board part]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

1 files changed, 80 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
new file mode 100644
index 000000000000..9ac1043e25bc
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_H__
+
+/* CPG */
+#define R8A7794_CLK_MAIN                0
+#define R8A7794_CLK_PLL0                1
+#define R8A7794_CLK_PLL1                2
+#define R8A7794_CLK_PLL3                3
+#define R8A7794_CLK_LB                  4
+#define R8A7794_CLK_QSPI                5
+#define R8A7794_CLK_SDH                 6
+#define R8A7794_CLK_SD0                 7
+#define R8A7794_CLK_Z                   8
+
+/* MSTP0 */
+#define R8A7794_CLK_MSIOF0              0
+
+/* MSTP1 */
+#define R8A7794_CLK_TMU1                11
+#define R8A7794_CLK_TMU3                21
+#define R8A7794_CLK_TMU2                22
+#define R8A7794_CLK_CMT0                24
+#define R8A7794_CLK_TMU0                25
+
+/* MSTP2 */
+#define R8A7794_CLK_SCIFA2              2
+#define R8A7794_CLK_SCIFA1              3
+#define R8A7794_CLK_SCIFA0              4
+#define R8A7794_CLK_MSIOF2              5
+#define R8A7794_CLK_SCIFB0              6
+#define R8A7794_CLK_SCIFB1              7
+#define R8A7794_CLK_MSIOF1              8
+#define R8A7794_CLK_SCIFB2              16
+
+/* MSTP3 */
+#define R8A7794_CLK_CMT1                29
+
+/* MSTP5 */
+#define R8A7794_CLK_THERMAL             22
+#define R8A7794_CLK_PWM                 23
+
+/* MSTP7 */
+#define R8A7794_CLK_HSCIF2              13
+#define R8A7794_CLK_SCIF5               14
+#define R8A7794_CLK_SCIF4               15
+#define R8A7794_CLK_HSCIF1              16
+#define R8A7794_CLK_HSCIF0              17
+#define R8A7794_CLK_SCIF3               18
+#define R8A7794_CLK_SCIF2               19
+#define R8A7794_CLK_SCIF1               20
+#define R8A7794_CLK_SCIF0               21
+
+/* MSTP8 */
+#define R8A7794_CLK_ETHER               13
+
+/* MSTP9 */
+#define R8A7794_CLK_GPIO6               5
+#define R8A7794_CLK_GPIO5               7
+#define R8A7794_CLK_GPIO4               8
+#define R8A7794_CLK_GPIO3               9
+#define R8A7794_CLK_GPIO2               10
+#define R8A7794_CLK_GPIO1               11
+#define R8A7794_CLK_GPIO0               12
+
+/* MSTP11 */
+#define R8A7794_CLK_SCIFA3              6
+#define R8A7794_CLK_SCIFA4              7
+#define R8A7794_CLK_SCIFA5              8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */