clk: samsung: exynos5433: Move CLK_SCLK_HDMI_SPDIF_DISP clock to CMU_TOP domain

This patch fixes the bug of CLK_SCLK_HDMI_SPDIF_DISP clock because this clock
should be included in CMU_TOP domain. So, this patch moves the CLK_SCLK_HDMI_
SPDIF_DISP clock from CMU_MIF to CMU_TOP domain.

Reported-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 4853bc598b57..5bd80d5ecd0f 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -189,8 +189,9 @@
 #define CLK_SCLK_ISP_UART_CAM1          250
 #define CLK_SCLK_ISP_SPI1_CAM1          251
 #define CLK_SCLK_ISP_SPI0_CAM1          252
+#define CLK_SCLK_HDMI_SPDIF_DISP        253
 
-#define TOP_NR_CLK                      253
+#define TOP_NR_CLK                      254
 
 /* CMU_CPIF */
 #define CLK_FOUT_MPHY_PLL               1
@@ -397,9 +398,8 @@
 #define CLK_SCLK_BUS_PLL                198
 #define CLK_SCLK_BUS_PLL_APOLLO         199
 #define CLK_SCLK_BUS_PLL_ATLAS          200
-#define CLK_SCLK_HDMI_SPDIF_DISP        201
 
-#define MIF_NR_CLK                      202
+#define MIF_NR_CLK                      201
 
 /* CMU_PERIC */
 #define CLK_PCLK_SPI2                   1