Merge tag 'imx-soc-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt

This is a dependency for imx/dt

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

2 files changed, 311 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
new file mode 100644
index 000000000000..7fcdf90879f2
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
+#define __DT_BINDINGS_CLOCK_IMX6SL_H
+
+#define IMX6SL_CLK_DUMMY                0
+#define IMX6SL_CLK_CKIL                 1
+#define IMX6SL_CLK_OSC                  2
+#define IMX6SL_CLK_PLL1_SYS             3
+#define IMX6SL_CLK_PLL2_BUS             4
+#define IMX6SL_CLK_PLL3_USB_OTG         5
+#define IMX6SL_CLK_PLL4_AUDIO           6
+#define IMX6SL_CLK_PLL5_VIDEO           7
+#define IMX6SL_CLK_PLL6_ENET            8
+#define IMX6SL_CLK_PLL7_USB_HOST        9
+#define IMX6SL_CLK_USBPHY1              10
+#define IMX6SL_CLK_USBPHY2              11
+#define IMX6SL_CLK_USBPHY1_GATE         12
+#define IMX6SL_CLK_USBPHY2_GATE         13
+#define IMX6SL_CLK_PLL4_POST_DIV        14
+#define IMX6SL_CLK_PLL5_POST_DIV        15
+#define IMX6SL_CLK_PLL5_VIDEO_DIV       16
+#define IMX6SL_CLK_ENET_REF             17
+#define IMX6SL_CLK_PLL2_PFD0            18
+#define IMX6SL_CLK_PLL2_PFD1            19
+#define IMX6SL_CLK_PLL2_PFD2            20
+#define IMX6SL_CLK_PLL3_PFD0            21
+#define IMX6SL_CLK_PLL3_PFD1            22
+#define IMX6SL_CLK_PLL3_PFD2            23
+#define IMX6SL_CLK_PLL3_PFD3            24
+#define IMX6SL_CLK_PLL2_198M            25
+#define IMX6SL_CLK_PLL3_120M            26
+#define IMX6SL_CLK_PLL3_80M             27
+#define IMX6SL_CLK_PLL3_60M             28
+#define IMX6SL_CLK_STEP                 29
+#define IMX6SL_CLK_PLL1_SW              30
+#define IMX6SL_CLK_OCRAM_ALT_SEL        31
+#define IMX6SL_CLK_OCRAM_SEL            32
+#define IMX6SL_CLK_PRE_PERIPH2_SEL      33
+#define IMX6SL_CLK_PRE_PERIPH_SEL       34
+#define IMX6SL_CLK_PERIPH2_CLK2_SEL     35
+#define IMX6SL_CLK_PERIPH_CLK2_SEL      36
+#define IMX6SL_CLK_CSI_SEL              37
+#define IMX6SL_CLK_LCDIF_AXI_SEL        38
+#define IMX6SL_CLK_USDHC1_SEL           39
+#define IMX6SL_CLK_USDHC2_SEL           40
+#define IMX6SL_CLK_USDHC3_SEL           41
+#define IMX6SL_CLK_USDHC4_SEL           42
+#define IMX6SL_CLK_SSI1_SEL             43
+#define IMX6SL_CLK_SSI2_SEL             44
+#define IMX6SL_CLK_SSI3_SEL             45
+#define IMX6SL_CLK_PERCLK_SEL           46
+#define IMX6SL_CLK_PXP_AXI_SEL          47
+#define IMX6SL_CLK_EPDC_AXI_SEL         48
+#define IMX6SL_CLK_GPU2D_OVG_SEL        49
+#define IMX6SL_CLK_GPU2D_SEL            50
+#define IMX6SL_CLK_LCDIF_PIX_SEL        51
+#define IMX6SL_CLK_EPDC_PIX_SEL         52
+#define IMX6SL_CLK_SPDIF0_SEL           53
+#define IMX6SL_CLK_SPDIF1_SEL           54
+#define IMX6SL_CLK_EXTERN_AUDIO_SEL     55
+#define IMX6SL_CLK_ECSPI_SEL            56
+#define IMX6SL_CLK_UART_SEL             57
+#define IMX6SL_CLK_PERIPH               58
+#define IMX6SL_CLK_PERIPH2              59
+#define IMX6SL_CLK_OCRAM_PODF           60
+#define IMX6SL_CLK_PERIPH_CLK2_PODF     61
+#define IMX6SL_CLK_PERIPH2_CLK2_PODF    62
+#define IMX6SL_CLK_IPG                  63
+#define IMX6SL_CLK_CSI_PODF             64
+#define IMX6SL_CLK_LCDIF_AXI_PODF       65
+#define IMX6SL_CLK_USDHC1_PODF          66
+#define IMX6SL_CLK_USDHC2_PODF          67
+#define IMX6SL_CLK_USDHC3_PODF          68
+#define IMX6SL_CLK_USDHC4_PODF          69
+#define IMX6SL_CLK_SSI1_PRED            70
+#define IMX6SL_CLK_SSI1_PODF            71
+#define IMX6SL_CLK_SSI2_PRED            72
+#define IMX6SL_CLK_SSI2_PODF            73
+#define IMX6SL_CLK_SSI3_PRED            74
+#define IMX6SL_CLK_SSI3_PODF            75
+#define IMX6SL_CLK_PERCLK               76
+#define IMX6SL_CLK_PXP_AXI_PODF         77
+#define IMX6SL_CLK_EPDC_AXI_PODF        78
+#define IMX6SL_CLK_GPU2D_OVG_PODF       79
+#define IMX6SL_CLK_GPU2D_PODF           80
+#define IMX6SL_CLK_LCDIF_PIX_PRED       81
+#define IMX6SL_CLK_EPDC_PIX_PRED        82
+#define IMX6SL_CLK_LCDIF_PIX_PODF       83
+#define IMX6SL_CLK_EPDC_PIX_PODF        84
+#define IMX6SL_CLK_SPDIF0_PRED          85
+#define IMX6SL_CLK_SPDIF0_PODF          86
+#define IMX6SL_CLK_SPDIF1_PRED          87
+#define IMX6SL_CLK_SPDIF1_PODF          88
+#define IMX6SL_CLK_EXTERN_AUDIO_PRED    89
+#define IMX6SL_CLK_EXTERN_AUDIO_PODF    90
+#define IMX6SL_CLK_ECSPI_ROOT           91
+#define IMX6SL_CLK_UART_ROOT            92
+#define IMX6SL_CLK_AHB                  93
+#define IMX6SL_CLK_MMDC_ROOT            94
+#define IMX6SL_CLK_ARM                  95
+#define IMX6SL_CLK_ECSPI1               96
+#define IMX6SL_CLK_ECSPI2               97
+#define IMX6SL_CLK_ECSPI3               98
+#define IMX6SL_CLK_ECSPI4               99
+#define IMX6SL_CLK_EPIT1                100
+#define IMX6SL_CLK_EPIT2                101
+#define IMX6SL_CLK_EXTERN_AUDIO         102
+#define IMX6SL_CLK_GPT                  103
+#define IMX6SL_CLK_GPT_SERIAL           104
+#define IMX6SL_CLK_GPU2D_OVG            105
+#define IMX6SL_CLK_I2C1                 106
+#define IMX6SL_CLK_I2C2                 107
+#define IMX6SL_CLK_I2C3                 108
+#define IMX6SL_CLK_OCOTP                109
+#define IMX6SL_CLK_CSI                  110
+#define IMX6SL_CLK_PXP_AXI              111
+#define IMX6SL_CLK_EPDC_AXI             112
+#define IMX6SL_CLK_LCDIF_AXI            113
+#define IMX6SL_CLK_LCDIF_PIX            114
+#define IMX6SL_CLK_EPDC_PIX             115
+#define IMX6SL_CLK_OCRAM                116
+#define IMX6SL_CLK_PWM1                 117
+#define IMX6SL_CLK_PWM2                 118
+#define IMX6SL_CLK_PWM3                 119
+#define IMX6SL_CLK_PWM4                 120
+#define IMX6SL_CLK_SDMA                 121
+#define IMX6SL_CLK_SPDIF                122
+#define IMX6SL_CLK_SSI1                 123
+#define IMX6SL_CLK_SSI2                 124
+#define IMX6SL_CLK_SSI3                 125
+#define IMX6SL_CLK_UART                 126
+#define IMX6SL_CLK_UART_SERIAL          127
+#define IMX6SL_CLK_USBOH3               128
+#define IMX6SL_CLK_USDHC1               129
+#define IMX6SL_CLK_USDHC2               130
+#define IMX6SL_CLK_USDHC3               131
+#define IMX6SL_CLK_USDHC4               132
+#define IMX6SL_CLK_CLK_END              133
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
new file mode 100644
index 000000000000..15e997fa78f2
--- /dev/null
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_VF610_H
+#define __DT_BINDINGS_CLOCK_VF610_H
+
+#define VF610_CLK_DUMMY                 0
+#define VF610_CLK_SIRC_128K             1
+#define VF610_CLK_SIRC_32K              2
+#define VF610_CLK_FIRC                  3
+#define VF610_CLK_SXOSC                 4
+#define VF610_CLK_FXOSC                 5
+#define VF610_CLK_FXOSC_HALF            6
+#define VF610_CLK_SLOW_CLK_SEL          7
+#define VF610_CLK_FASK_CLK_SEL          8
+#define VF610_CLK_AUDIO_EXT             9
+#define VF610_CLK_ENET_EXT              10
+#define VF610_CLK_PLL1_MAIN             11
+#define VF610_CLK_PLL1_PFD1             12
+#define VF610_CLK_PLL1_PFD2             13
+#define VF610_CLK_PLL1_PFD3             14
+#define VF610_CLK_PLL1_PFD4             15
+#define VF610_CLK_PLL2_MAIN             16
+#define VF610_CLK_PLL2_PFD1             17
+#define VF610_CLK_PLL2_PFD2             18
+#define VF610_CLK_PLL2_PFD3             19
+#define VF610_CLK_PLL2_PFD4             20
+#define VF610_CLK_PLL3_MAIN             21
+#define VF610_CLK_PLL3_PFD1             22
+#define VF610_CLK_PLL3_PFD2             23
+#define VF610_CLK_PLL3_PFD3             24
+#define VF610_CLK_PLL3_PFD4             25
+#define VF610_CLK_PLL4_MAIN             26
+#define VF610_CLK_PLL5_MAIN             27
+#define VF610_CLK_PLL6_MAIN             28
+#define VF610_CLK_PLL3_MAIN_DIV         29
+#define VF610_CLK_PLL4_MAIN_DIV         30
+#define VF610_CLK_PLL6_MAIN_DIV         31
+#define VF610_CLK_PLL1_PFD_SEL          32
+#define VF610_CLK_PLL2_PFD_SEL          33
+#define VF610_CLK_SYS_SEL               34
+#define VF610_CLK_DDR_SEL               35
+#define VF610_CLK_SYS_BUS               36
+#define VF610_CLK_PLATFORM_BUS          37
+#define VF610_CLK_IPG_BUS               38
+#define VF610_CLK_UART0                 39
+#define VF610_CLK_UART1                 40
+#define VF610_CLK_UART2                 41
+#define VF610_CLK_UART3                 42
+#define VF610_CLK_UART4                 43
+#define VF610_CLK_UART5                 44
+#define VF610_CLK_PIT                   45
+#define VF610_CLK_I2C0                  46
+#define VF610_CLK_I2C1                  47
+#define VF610_CLK_I2C2                  48
+#define VF610_CLK_I2C3                  49
+#define VF610_CLK_FTM0_EXT_SEL          50
+#define VF610_CLK_FTM0_FIX_SEL          51
+#define VF610_CLK_FTM0_EXT_FIX_EN       52
+#define VF610_CLK_FTM1_EXT_SEL          53
+#define VF610_CLK_FTM1_FIX_SEL          54
+#define VF610_CLK_FTM1_EXT_FIX_EN       55
+#define VF610_CLK_FTM2_EXT_SEL          56
+#define VF610_CLK_FTM2_FIX_SEL          57
+#define VF610_CLK_FTM2_EXT_FIX_EN       58
+#define VF610_CLK_FTM3_EXT_SEL          59
+#define VF610_CLK_FTM3_FIX_SEL          60
+#define VF610_CLK_FTM3_EXT_FIX_EN       61
+#define VF610_CLK_FTM0                  62
+#define VF610_CLK_FTM1                  63
+#define VF610_CLK_FTM2                  64
+#define VF610_CLK_FTM3                  65
+#define VF610_CLK_ENET_50M              66
+#define VF610_CLK_ENET_25M              67
+#define VF610_CLK_ENET_SEL              68
+#define VF610_CLK_ENET                  69
+#define VF610_CLK_ENET_TS_SEL           70
+#define VF610_CLK_ENET_TS               71
+#define VF610_CLK_DSPI0                 72
+#define VF610_CLK_DSPI1                 73
+#define VF610_CLK_DSPI2                 74
+#define VF610_CLK_DSPI3                 75
+#define VF610_CLK_WDT                   76
+#define VF610_CLK_ESDHC0_SEL            77
+#define VF610_CLK_ESDHC0_EN             78
+#define VF610_CLK_ESDHC0_DIV            79
+#define VF610_CLK_ESDHC0                80
+#define VF610_CLK_ESDHC1_SEL            81
+#define VF610_CLK_ESDHC1_EN             82
+#define VF610_CLK_ESDHC1_DIV            83
+#define VF610_CLK_ESDHC1                84
+#define VF610_CLK_DCU0_SEL              85
+#define VF610_CLK_DCU0_EN               86
+#define VF610_CLK_DCU0_DIV              87
+#define VF610_CLK_DCU0                  88
+#define VF610_CLK_DCU1_SEL              89
+#define VF610_CLK_DCU1_EN               90
+#define VF610_CLK_DCU1_DIV              91
+#define VF610_CLK_DCU1                  92
+#define VF610_CLK_ESAI_SEL              93
+#define VF610_CLK_ESAI_EN               94
+#define VF610_CLK_ESAI_DIV              95
+#define VF610_CLK_ESAI                  96
+#define VF610_CLK_SAI0_SEL              97
+#define VF610_CLK_SAI0_EN               98
+#define VF610_CLK_SAI0_DIV              99
+#define VF610_CLK_SAI0                  100
+#define VF610_CLK_SAI1_SEL              101
+#define VF610_CLK_SAI1_EN               102
+#define VF610_CLK_SAI1_DIV              103
+#define VF610_CLK_SAI1                  104
+#define VF610_CLK_SAI2_SEL              105
+#define VF610_CLK_SAI2_EN               106
+#define VF610_CLK_SAI2_DIV              107
+#define VF610_CLK_SAI2                  108
+#define VF610_CLK_SAI3_SEL              109
+#define VF610_CLK_SAI3_EN               110
+#define VF610_CLK_SAI3_DIV              111
+#define VF610_CLK_SAI3                  112
+#define VF610_CLK_USBC0                 113
+#define VF610_CLK_USBC1                 114
+#define VF610_CLK_QSPI0_SEL             115
+#define VF610_CLK_QSPI0_EN              116
+#define VF610_CLK_QSPI0_X4_DIV          117
+#define VF610_CLK_QSPI0_X2_DIV          118
+#define VF610_CLK_QSPI0_X1_DIV          119
+#define VF610_CLK_QSPI1_SEL             120
+#define VF610_CLK_QSPI1_EN              121
+#define VF610_CLK_QSPI1_X4_DIV          122
+#define VF610_CLK_QSPI1_X2_DIV          123
+#define VF610_CLK_QSPI1_X1_DIV          124
+#define VF610_CLK_QSPI0                 125
+#define VF610_CLK_QSPI1                 126
+#define VF610_CLK_NFC_SEL               127
+#define VF610_CLK_NFC_EN                128
+#define VF610_CLK_NFC_PRE_DIV           129
+#define VF610_CLK_NFC_FRAC_DIV          130
+#define VF610_CLK_NFC_INV               131
+#define VF610_CLK_NFC                   132
+#define VF610_CLK_VADC_SEL              133
+#define VF610_CLK_VADC_EN               134
+#define VF610_CLK_VADC_DIV              135
+#define VF610_CLK_VADC_DIV_HALF         136
+#define VF610_CLK_VADC                  137
+#define VF610_CLK_ADC0                  138
+#define VF610_CLK_ADC1                  139
+#define VF610_CLK_DAC0                  140
+#define VF610_CLK_DAC1                  141
+#define VF610_CLK_FLEXCAN0              142
+#define VF610_CLK_FLEXCAN1              143
+#define VF610_CLK_ASRC                  144
+#define VF610_CLK_GPU_SEL               145
+#define VF610_CLK_GPU_EN                146
+#define VF610_CLK_GPU2D                 147
+#define VF610_CLK_END                   148
+
+#endif /* __DT_BINDINGS_CLOCK_VF610_H */