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authorOlof Johansson <olof@lixom.net>2014-07-19 18:03:08 -0400
committerOlof Johansson <olof@lixom.net>2014-07-19 18:03:08 -0400
commitf37ac9e5a47d72eab5185b0ddc14dfc943cc9589 (patch)
tree53577aa529e3bbe718459d0626fc6d45ada3dcdd /include/dt-bindings
parent4338925434e4bf5ff714055713f3fb9b5fae9037 (diff)
parentfc2cac41ebbfb16da8b036cba6ec6714ab780a6d (diff)
Merge tag 'exynos-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Merge "Samsung exynos cpuidle update for v3.17" from Kukjin Kim: - add callbacks exynos_suspend() and exynos_powered_up() for support cpuidle through mcpm - skip exynos_cpuidle for exynos5420 because is uses cpuidle-big-liggle generic cpuidle driver - add generic functions to calculate cpu number is used for pmu and this is required for exynos5420 multi-cluster - add of_device_id structure for big.LITTLE cpuidle and add "samsung,exynos5420" compatible string for exynos5420 * tag 'exynos-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: populate suspend and powered_up callbacks for mcpm ARM: EXYNOS: do not allow cpuidle registration for exynos5420 cpuidle: big.LITTLE: init driver for exynos5420 cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config ARM: EXYNOS: add generic function to calculate cpu number cpuidle: big.LITTLE: add of_device_id structure + Linux 3.16-rc5 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/exynos5420.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 97dcb89d37d3..21d51ae1d242 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -63,7 +63,6 @@
63#define CLK_SCLK_MPHY_IXTAL24 161 63#define CLK_SCLK_MPHY_IXTAL24 161
64 64
65/* gate clocks */ 65/* gate clocks */
66#define CLK_ACLK66_PERIC 256
67#define CLK_UART0 257 66#define CLK_UART0 257
68#define CLK_UART1 258 67#define CLK_UART1 258
69#define CLK_UART2 259 68#define CLK_UART2 259
@@ -203,6 +202,8 @@
203#define CLK_MOUT_G3D 641 202#define CLK_MOUT_G3D 641
204#define CLK_MOUT_VPLL 642 203#define CLK_MOUT_VPLL 642
205#define CLK_MOUT_MAUDIO0 643 204#define CLK_MOUT_MAUDIO0 643
205#define CLK_MOUT_USER_ACLK333 644
206#define CLK_MOUT_SW_ACLK333 645
206 207
207/* divider clocks */ 208/* divider clocks */
208#define CLK_DOUT_PIXEL 768 209#define CLK_DOUT_PIXEL 768