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authorLinus Torvalds <torvalds@linux-foundation.org>2014-12-11 13:43:14 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-12-11 13:43:14 -0500
commitc1b30e4d9466000c0e287e9245d4397da4d7d2f9 (patch)
tree18ac4c6bb435202cee8e7281f58b0c72f7fa0144 /include/dt-bindings
parent92a578b064d0227a3a7fbbdb9e29dbab7f8d400e (diff)
parent853b6bf044dcced57c523dbddabf8942e907be6e (diff)
Merge tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control changes from Linus Walleij: "Here is a stash of pin control changes I have collected for the v3.19 series. Mainly new hardware support, with Intels new embedded SoC as the especially interesting thing standing out, fully using the subsystem. - Force conversion of the ux500 pin control device trees and parsers to use the generic pin control bindings. - New driver and device tree bindings for the Qualcomm PMIC MPP pin controller and GPIO. - Some ACPI infrastructure for pin controllers. - New driver for the Intel CherryView/Braswell pin controller, the first Intel pin controller to fully take advantage of the pin control subsystem. - Support the Freescale i.MX VF610 variant. - Support the sunxi A80 variant. - Support the Samsung Exynos 4415 and Exynos 7 variants. - Split out Intel pin controllers to their own subdirectory. - A large slew of rockchip pin control updates, including suspend/resume support. - A large slew of Samsung Exynos pin controller updates. - Various minor updates and fixes" * tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (49 commits) pinctrl: at91: enhance (debugfs) at91_gpio_dbg_show pinctrl: meson: add device tree bindings documentation gpio: tz1090: Fix error handling of irq_of_parse_and_map pinctrl: tz1090-pinctrl.txt: Fix typo in binding pinctrl: pinconf-generic: Declare dt_params/conf_items const pinctrl: exynos: Add support for Exynos4415 pinctrl: exynos: Add initial driver data for Exynos7 pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts pinctrl: exynos: Consolidate irq domain callbacks pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: samsung: Separate per-bank init and runtime data pinctrl: samsung: Constify samsung_pin_ctrl struct pinctrl: samsung: Constify samsung_pin_bank_type struct pinctrl: samsung: Drop unused label field in samsung_pin_ctrl struct pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR() pinctrl: Add Intel Cherryview/Braswell pin controller support gpio / ACPI: Add knowledge about pin controllers to acpi_get_gpiod() pinctrl: Fix path error in documentation pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume pinctrl: rockchip: add suspend/resume functions ...
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/pinctrl/qcom,pmic-gpio.h142
-rw-r--r--include/dt-bindings/pinctrl/qcom,pmic-mpp.h44
2 files changed, 186 insertions, 0 deletions
diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
new file mode 100644
index 000000000000..fa74d7cc960c
--- /dev/null
+++ b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
@@ -0,0 +1,142 @@
1/*
2 * This header provides constants for the Qualcomm PMIC GPIO binding.
3 */
4
5#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
6#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
7
8#define PMIC_GPIO_PULL_UP_30 0
9#define PMIC_GPIO_PULL_UP_1P5 1
10#define PMIC_GPIO_PULL_UP_31P5 2
11#define PMIC_GPIO_PULL_UP_1P5_30 3
12
13#define PMIC_GPIO_STRENGTH_NO 0
14#define PMIC_GPIO_STRENGTH_HIGH 1
15#define PMIC_GPIO_STRENGTH_MED 2
16#define PMIC_GPIO_STRENGTH_LOW 3
17
18/*
19 * Note: PM8018 GPIO3 and GPIO4 are supporting
20 * only S3 and L2 options (1.8V)
21 */
22#define PM8018_GPIO_L6 0
23#define PM8018_GPIO_L5 1
24#define PM8018_GPIO_S3 2
25#define PM8018_GPIO_L14 3
26#define PM8018_GPIO_L2 4
27#define PM8018_GPIO_L4 5
28#define PM8018_GPIO_VDD 6
29
30/*
31 * Note: PM8038 GPIO7 and GPIO8 are supporting
32 * only L11 and L4 options (1.8V)
33 */
34#define PM8038_GPIO_VPH 0
35#define PM8038_GPIO_BB 1
36#define PM8038_GPIO_L11 2
37#define PM8038_GPIO_L15 3
38#define PM8038_GPIO_L4 4
39#define PM8038_GPIO_L3 5
40#define PM8038_GPIO_L17 6
41
42#define PM8058_GPIO_VPH 0
43#define PM8058_GPIO_BB 1
44#define PM8058_GPIO_S3 2
45#define PM8058_GPIO_L3 3
46#define PM8058_GPIO_L7 4
47#define PM8058_GPIO_L6 5
48#define PM8058_GPIO_L5 6
49#define PM8058_GPIO_L2 7
50
51#define PM8917_GPIO_VPH 0
52#define PM8917_GPIO_S4 2
53#define PM8917_GPIO_L15 3
54#define PM8917_GPIO_L4 4
55#define PM8917_GPIO_L3 5
56#define PM8917_GPIO_L17 6
57
58#define PM8921_GPIO_VPH 0
59#define PM8921_GPIO_BB 1
60#define PM8921_GPIO_S4 2
61#define PM8921_GPIO_L15 3
62#define PM8921_GPIO_L4 4
63#define PM8921_GPIO_L3 5
64#define PM8921_GPIO_L17 6
65
66/*
67 * Note: PM8941 gpios from 15 to 18 are supporting
68 * only S3 and L6 options (1.8V)
69 */
70#define PM8941_GPIO_VPH 0
71#define PM8941_GPIO_L1 1
72#define PM8941_GPIO_S3 2
73#define PM8941_GPIO_L6 3
74
75/*
76 * Note: PMA8084 gpios from 15 to 18 are supporting
77 * only S4 and L6 options (1.8V)
78 */
79#define PMA8084_GPIO_VPH 0
80#define PMA8084_GPIO_L1 1
81#define PMA8084_GPIO_S4 2
82#define PMA8084_GPIO_L6 3
83
84/* To be used with "function" */
85#define PMIC_GPIO_FUNC_NORMAL "normal"
86#define PMIC_GPIO_FUNC_PAIRED "paired"
87#define PMIC_GPIO_FUNC_FUNC1 "func1"
88#define PMIC_GPIO_FUNC_FUNC2 "func2"
89#define PMIC_GPIO_FUNC_DTEST1 "dtest1"
90#define PMIC_GPIO_FUNC_DTEST2 "dtest2"
91#define PMIC_GPIO_FUNC_DTEST3 "dtest3"
92#define PMIC_GPIO_FUNC_DTEST4 "dtest4"
93
94#define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1
95#define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1
96#define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1
97#define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1
98#define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1
99#define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1
100#define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
101#define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2
102
103#define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1
104#define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2
105#define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1
106#define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2
107#define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2
108#define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1
109#define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1
110#define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1
111#define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1
112#define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2
113#define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1
114#define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2
115#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1
116#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1
117
118#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1
119#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
120#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2
121#define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1
122#define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1
123#define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2
124
125#define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1
126#define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1
127#define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2
128#define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1
129#define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2
130#define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
131#define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1
132#define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2
133
134#define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1
135#define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1
136#define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2
137#define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2
138#define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1
139#define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2
140#define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
141
142#endif
diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
new file mode 100644
index 000000000000..d2c7dabe3223
--- /dev/null
+++ b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
@@ -0,0 +1,44 @@
1/*
2 * This header provides constants for the Qualcomm PMIC's
3 * Multi-Purpose Pin binding.
4 */
5
6#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
7#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
8
9/* power-source */
10#define PM8841_MPP_VPH 0
11#define PM8841_MPP_S3 2
12
13#define PM8941_MPP_VPH 0
14#define PM8941_MPP_L1 1
15#define PM8941_MPP_S3 2
16#define PM8941_MPP_L6 3
17
18#define PMA8084_MPP_VPH 0
19#define PMA8084_MPP_L1 1
20#define PMA8084_MPP_S4 2
21#define PMA8084_MPP_L6 3
22
23/*
24 * Analog Input - Set the source for analog input.
25 * To be used with "qcom,amux-route" property
26 */
27#define PMIC_MPP_AMUX_ROUTE_CH5 0
28#define PMIC_MPP_AMUX_ROUTE_CH6 1
29#define PMIC_MPP_AMUX_ROUTE_CH7 2
30#define PMIC_MPP_AMUX_ROUTE_CH8 3
31#define PMIC_MPP_AMUX_ROUTE_ABUS1 4
32#define PMIC_MPP_AMUX_ROUTE_ABUS2 5
33#define PMIC_MPP_AMUX_ROUTE_ABUS3 6
34#define PMIC_MPP_AMUX_ROUTE_ABUS4 7
35
36/* To be used with "function" */
37#define PMIC_MPP_FUNC_NORMAL "normal"
38#define PMIC_MPP_FUNC_PAIRED "paired"
39#define PMIC_MPP_FUNC_DTEST1 "dtest1"
40#define PMIC_MPP_FUNC_DTEST2 "dtest2"
41#define PMIC_MPP_FUNC_DTEST3 "dtest3"
42#define PMIC_MPP_FUNC_DTEST4 "dtest4"
43
44#endif