Merge branch 'topic/enum-info-cleanup' into for-next

this is a series of patches to just convert the plain info callback
for enum ctl elements to snd_ctl_elem_info().  Also, it includes the
extension of snd_ctl_elem_info(), for catching the unexpected string
cut-off and handling the zero items.

21 files changed, 572 insertions, 13 deletions

diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index b535e9da7de6..961b9c130ea9 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -255,4 +255,31 @@
  */
 #define CLK_NR_CLKS                     248
 
+/*
+ * CMU DMC
+ */
+
+#define CLK_FOUT_BPLL                   1
+#define CLK_FOUT_EPLL                   2
+
+/* Muxes */
+#define CLK_MOUT_MPLL_MIF               8
+#define CLK_MOUT_BPLL                   9
+#define CLK_MOUT_DPHY                   10
+#define CLK_MOUT_DMC_BUS                11
+#define CLK_MOUT_EPLL                   12
+
+/* Dividers */
+#define CLK_DIV_DMC                     16
+#define CLK_DIV_DPHY                    17
+#define CLK_DIV_DMC_PRE                 18
+#define CLK_DIV_DMCP                    19
+#define CLK_DIV_DMCD                    20
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define NR_CLKS_DMC                     21
+
 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 459bd2bd411f..34fe28c622d0 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -115,11 +115,11 @@
 #define CLK_SMMU_MFCR           275
 #define CLK_G3D                 276
 #define CLK_G2D                 277
-#define CLK_ROTATOR             278 /* Exynos4210 only */
-#define CLK_MDMA                279 /* Exynos4210 only */
-#define CLK_SMMU_G2D            280 /* Exynos4210 only */
-#define CLK_SMMU_ROTATOR        281 /* Exynos4210 only */
-#define CLK_SMMU_MDMA           282 /* Exynos4210 only */
+#define CLK_ROTATOR             278
+#define CLK_MDMA                279
+#define CLK_SMMU_G2D            280
+#define CLK_SMMU_ROTATOR        281
+#define CLK_SMMU_MDMA           282
 #define CLK_FIMD0               283
 #define CLK_MIE0                284
 #define CLK_MDNIE0              285 /* Exynos4412 only */
@@ -234,6 +234,8 @@
 #define CLK_MOUT_G3D1           393
 #define CLK_MOUT_G3D            394
 #define CLK_ACLK400_MCUISP      395 /* Exynos4x12 only */
+#define CLK_MOUT_HDMI           396
+#define CLK_MOUT_MIXER          397
 
 /* gate clocks - ppmu */
 #define CLK_PPMULEFT            400
diff --git a/include/dt-bindings/clock/hix5hd2-clock.h b/include/dt-bindings/clock/hix5hd2-clock.h
index aad579a75802..fd29c174ba63 100644
--- a/include/dt-bindings/clock/hix5hd2-clock.h
+++ b/include/dt-bindings/clock/hix5hd2-clock.h
@@ -46,6 +46,7 @@
 #define HIX5HD2_SFC_MUX                 64
 #define HIX5HD2_MMC_MUX                 65
 #define HIX5HD2_FEPHY_MUX               66
+#define HIX5HD2_SD_MUX                  67
 
 /* gate clocks */
 #define HIX5HD2_SFC_RST                 128
@@ -53,6 +54,32 @@
 #define HIX5HD2_MMC_CIU_CLK             130
 #define HIX5HD2_MMC_BIU_CLK             131
 #define HIX5HD2_MMC_CIU_RST             132
+#define HIX5HD2_FWD_BUS_CLK             133
+#define HIX5HD2_FWD_SYS_CLK             134
+#define HIX5HD2_MAC0_PHY_CLK            135
+#define HIX5HD2_SD_CIU_CLK              136
+#define HIX5HD2_SD_BIU_CLK              137
+#define HIX5HD2_SD_CIU_RST              138
+#define HIX5HD2_WDG0_CLK                139
+#define HIX5HD2_WDG0_RST                140
+#define HIX5HD2_I2C0_CLK                141
+#define HIX5HD2_I2C0_RST                142
+#define HIX5HD2_I2C1_CLK                143
+#define HIX5HD2_I2C1_RST                144
+#define HIX5HD2_I2C2_CLK                145
+#define HIX5HD2_I2C2_RST                146
+#define HIX5HD2_I2C3_CLK                147
+#define HIX5HD2_I2C3_RST                148
+#define HIX5HD2_I2C4_CLK                149
+#define HIX5HD2_I2C4_RST                150
+#define HIX5HD2_I2C5_CLK                151
+#define HIX5HD2_I2C5_RST                152
+
+/* complex */
+#define HIX5HD2_MAC0_CLK                192
+#define HIX5HD2_MAC1_CLK                193
+#define HIX5HD2_SATA_CLK                194
+#define HIX5HD2_USB_CLK                 195
 
 #define HIX5HD2_NR_CLKS                 256
 #endif  /* __DTS_HIX5HD2_CLOCK_H */
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 654151e24288..ddaef8620b2c 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -128,7 +128,7 @@
 #define IMX6Q_CLK_ECSPI5                        116
 #define IMX6DL_CLK_I2C4                         116
 #define IMX6QDL_CLK_ENET                        117
-#define IMX6QDL_CLK_ESAI                        118
+#define IMX6QDL_CLK_ESAI_EXTAL                  118
 #define IMX6QDL_CLK_GPT_IPG                     119
 #define IMX6QDL_CLK_GPT_IPG_PER                 120
 #define IMX6QDL_CLK_GPU2D_CORE                  121
@@ -218,7 +218,36 @@
 #define IMX6QDL_CLK_LVDS2_SEL                   205
 #define IMX6QDL_CLK_LVDS1_GATE                  206
 #define IMX6QDL_CLK_LVDS2_GATE                  207
-#define IMX6QDL_CLK_ESAI_AHB                    208
-#define IMX6QDL_CLK_END                         209
+#define IMX6QDL_CLK_ESAI_IPG                    208
+#define IMX6QDL_CLK_ESAI_MEM                    209
+#define IMX6QDL_CLK_ASRC_IPG                    210
+#define IMX6QDL_CLK_ASRC_MEM                    211
+#define IMX6QDL_CLK_LVDS1_IN                    212
+#define IMX6QDL_CLK_LVDS2_IN                    213
+#define IMX6QDL_CLK_ANACLK1                     214
+#define IMX6QDL_CLK_ANACLK2                     215
+#define IMX6QDL_PLL1_BYPASS_SRC                 216
+#define IMX6QDL_PLL2_BYPASS_SRC                 217
+#define IMX6QDL_PLL3_BYPASS_SRC                 218
+#define IMX6QDL_PLL4_BYPASS_SRC                 219
+#define IMX6QDL_PLL5_BYPASS_SRC                 220
+#define IMX6QDL_PLL6_BYPASS_SRC                 221
+#define IMX6QDL_PLL7_BYPASS_SRC                 222
+#define IMX6QDL_CLK_PLL1                        223
+#define IMX6QDL_CLK_PLL2                        224
+#define IMX6QDL_CLK_PLL3                        225
+#define IMX6QDL_CLK_PLL4                        226
+#define IMX6QDL_CLK_PLL5                        227
+#define IMX6QDL_CLK_PLL6                        228
+#define IMX6QDL_CLK_PLL7                        229
+#define IMX6QDL_PLL1_BYPASS                     230
+#define IMX6QDL_PLL2_BYPASS                     231
+#define IMX6QDL_PLL3_BYPASS                     232
+#define IMX6QDL_PLL4_BYPASS                     233
+#define IMX6QDL_PLL5_BYPASS                     234
+#define IMX6QDL_PLL6_BYPASS                     235
+#define IMX6QDL_PLL7_BYPASS                     236
+#define IMX6QDL_CLK_GPT_3M                      237
+#define IMX6QDL_CLK_END                         238
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
index b91dd462ba85..9ce4e421096f 100644
--- a/include/dt-bindings/clock/imx6sl-clock.h
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -146,6 +146,34 @@
 #define IMX6SL_CLK_PLL4_AUDIO_DIV       133
 #define IMX6SL_CLK_SPBA                 134
 #define IMX6SL_CLK_ENET                 135
-#define IMX6SL_CLK_END                  136
+#define IMX6SL_CLK_LVDS1_SEL            136
+#define IMX6SL_CLK_LVDS1_OUT            137
+#define IMX6SL_CLK_LVDS1_IN             138
+#define IMX6SL_CLK_ANACLK1              139
+#define IMX6SL_PLL1_BYPASS_SRC          140
+#define IMX6SL_PLL2_BYPASS_SRC          141
+#define IMX6SL_PLL3_BYPASS_SRC          142
+#define IMX6SL_PLL4_BYPASS_SRC          143
+#define IMX6SL_PLL5_BYPASS_SRC          144
+#define IMX6SL_PLL6_BYPASS_SRC          145
+#define IMX6SL_PLL7_BYPASS_SRC          146
+#define IMX6SL_CLK_PLL1                 147
+#define IMX6SL_CLK_PLL2                 148
+#define IMX6SL_CLK_PLL3                 149
+#define IMX6SL_CLK_PLL4                 150
+#define IMX6SL_CLK_PLL5                 151
+#define IMX6SL_CLK_PLL6                 152
+#define IMX6SL_CLK_PLL7                 153
+#define IMX6SL_PLL1_BYPASS              154
+#define IMX6SL_PLL2_BYPASS              155
+#define IMX6SL_PLL3_BYPASS              156
+#define IMX6SL_PLL4_BYPASS              157
+#define IMX6SL_PLL5_BYPASS              158
+#define IMX6SL_PLL6_BYPASS              159
+#define IMX6SL_PLL7_BYPASS              160
+#define IMX6SL_CLK_SSI1_IPG             161
+#define IMX6SL_CLK_SSI2_IPG             162
+#define IMX6SL_CLK_SSI3_IPG             163
+#define IMX6SL_CLK_END                  164
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index 421d8bb76f2f..995709119ec5 100644
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -251,6 +251,29 @@
 #define IMX6SX_CLK_SAI2_IPG             238
 #define IMX6SX_CLK_ESAI_IPG             239
 #define IMX6SX_CLK_ESAI_MEM             240
-#define IMX6SX_CLK_CLK_END              241
+#define IMX6SX_CLK_LVDS1_IN             241
+#define IMX6SX_CLK_ANACLK1              242
+#define IMX6SX_PLL1_BYPASS_SRC          243
+#define IMX6SX_PLL2_BYPASS_SRC          244
+#define IMX6SX_PLL3_BYPASS_SRC          245
+#define IMX6SX_PLL4_BYPASS_SRC          246
+#define IMX6SX_PLL5_BYPASS_SRC          247
+#define IMX6SX_PLL6_BYPASS_SRC          248
+#define IMX6SX_PLL7_BYPASS_SRC          249
+#define IMX6SX_CLK_PLL1                 250
+#define IMX6SX_CLK_PLL2                 251
+#define IMX6SX_CLK_PLL3                 252
+#define IMX6SX_CLK_PLL4                 253
+#define IMX6SX_CLK_PLL5                 254
+#define IMX6SX_CLK_PLL6                 255
+#define IMX6SX_CLK_PLL7                 256
+#define IMX6SX_PLL1_BYPASS              257
+#define IMX6SX_PLL2_BYPASS              258
+#define IMX6SX_PLL3_BYPASS              259
+#define IMX6SX_PLL4_BYPASS              260
+#define IMX6SX_PLL5_BYPASS              261
+#define IMX6SX_PLL6_BYPASS              262
+#define IMX6SX_PLL7_BYPASS              263
+#define IMX6SX_CLK_CLK_END              264
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
diff --git a/include/dt-bindings/clock/maxim,max77686.h b/include/dt-bindings/clock/maxim,max77686.h
new file mode 100644
index 000000000000..7b28b0905869
--- /dev/null
+++ b/include/dt-bindings/clock/maxim,max77686.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77686 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77686_CLK_AP         0
+#define MAX77686_CLK_CP         1
+#define MAX77686_CLK_PMIC       2
+
+/* Total number of clocks. */
+#define MAX77686_CLKS_NUM               (MAX77686_CLK_PMIC + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H */
diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h
new file mode 100644
index 000000000000..997312edcbb5
--- /dev/null
+++ b/include/dt-bindings/clock/maxim,max77802.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77802 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77802_CLK_32K_AP             0
+#define MAX77802_CLK_32K_CP             1
+
+/* Total number of clocks. */
+#define MAX77802_CLKS_NUM               (MAX77802_CLK_32K_CP + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */
diff --git a/include/dt-bindings/clock/pxa-clock.h b/include/dt-bindings/clock/pxa-clock.h
new file mode 100644
index 000000000000..e65803b1dc7e
--- /dev/null
+++ b/include/dt-bindings/clock/pxa-clock.h
@@ -0,0 +1,77 @@
+/*
+ * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre
+ * Copyright (C) 2014 Robert Jarzmik
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__
+#define __DT_BINDINGS_CLOCK_PXA2XX_H__
+
+#define CLK_NONE 0
+#define CLK_1WIRE 1
+#define CLK_AC97 2
+#define CLK_AC97CONF 3
+#define CLK_ASSP 4
+#define CLK_BOOT 5
+#define CLK_BTUART 6
+#define CLK_CAMERA 7
+#define CLK_CIR 8
+#define CLK_CORE 9
+#define CLK_DMC 10
+#define CLK_FFUART 11
+#define CLK_FICP 12
+#define CLK_GPIO 13
+#define CLK_HSIO2 14
+#define CLK_HWUART 15
+#define CLK_I2C 16
+#define CLK_I2S 17
+#define CLK_IM 18
+#define CLK_INC 19
+#define CLK_ISC 20
+#define CLK_KEYPAD 21
+#define CLK_LCD 22
+#define CLK_MEMC 23
+#define CLK_MEMSTK 24
+#define CLK_MINI_IM 25
+#define CLK_MINI_LCD 26
+#define CLK_MMC 27
+#define CLK_MMC1 28
+#define CLK_MMC2 29
+#define CLK_MMC3 30
+#define CLK_MSL 31
+#define CLK_MSL0 32
+#define CLK_MVED 33
+#define CLK_NAND 34
+#define CLK_NSSP 35
+#define CLK_OSTIMER 36
+#define CLK_PWM0 37
+#define CLK_PWM1 38
+#define CLK_PWM2 39
+#define CLK_PWM3 40
+#define CLK_PWRI2C 41
+#define CLK_PXA300_GCU 42
+#define CLK_PXA320_GCU 43
+#define CLK_SMC 44
+#define CLK_SSP 45
+#define CLK_SSP1 46
+#define CLK_SSP2 47
+#define CLK_SSP3 48
+#define CLK_SSP4 49
+#define CLK_STUART 50
+#define CLK_TOUCH 51
+#define CLK_TPM 52
+#define CLK_UDC 53
+#define CLK_USB 54
+#define CLK_USB2 55
+#define CLK_USBH 56
+#define CLK_USBHOST 57
+#define CLK_USIM 58
+#define CLK_USIM1 59
+#define CLK_USMI0 60
+#define CLK_MAX 61
+
+#endif
diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-bindings/clock/r8a7740-clock.h
new file mode 100644
index 000000000000..f6b4b0fe7a43
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7740-clock.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2014 Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__
+#define __DT_BINDINGS_CLOCK_R8A7740_H__
+
+/* CPG */
+#define R8A7740_CLK_SYSTEM      0
+#define R8A7740_CLK_PLLC0       1
+#define R8A7740_CLK_PLLC1       2
+#define R8A7740_CLK_PLLC2       3
+#define R8A7740_CLK_R           4
+#define R8A7740_CLK_USB24S      5
+#define R8A7740_CLK_I           6
+#define R8A7740_CLK_ZG          7
+#define R8A7740_CLK_B           8
+#define R8A7740_CLK_M1          9
+#define R8A7740_CLK_HP          10
+#define R8A7740_CLK_HPP         11
+#define R8A7740_CLK_USBP        12
+#define R8A7740_CLK_S           13
+#define R8A7740_CLK_ZB          14
+#define R8A7740_CLK_M3          15
+#define R8A7740_CLK_CP          16
+
+/* MSTP1 */
+#define R8A7740_CLK_CEU21       28
+#define R8A7740_CLK_CEU20       27
+#define R8A7740_CLK_TMU0        25
+#define R8A7740_CLK_LCDC1       17
+#define R8A7740_CLK_IIC0        16
+#define R8A7740_CLK_TMU1        11
+#define R8A7740_CLK_LCDC0       0
+
+/* MSTP2 */
+#define R8A7740_CLK_SCIFA6      30
+#define R8A7740_CLK_SCIFA7      22
+#define R8A7740_CLK_DMAC1       18
+#define R8A7740_CLK_DMAC2       17
+#define R8A7740_CLK_DMAC3       16
+#define R8A7740_CLK_USBDMAC     14
+#define R8A7740_CLK_SCIFA5      7
+#define R8A7740_CLK_SCIFB       6
+#define R8A7740_CLK_SCIFA0      4
+#define R8A7740_CLK_SCIFA1      3
+#define R8A7740_CLK_SCIFA2      2
+#define R8A7740_CLK_SCIFA3      1
+#define R8A7740_CLK_SCIFA4      0
+
+/* MSTP3 */
+#define R8A7740_CLK_CMT1        29
+#define R8A7740_CLK_FSI         28
+#define R8A7740_CLK_IIC1        23
+#define R8A7740_CLK_USBF        20
+#define R8A7740_CLK_SDHI0       14
+#define R8A7740_CLK_SDHI1       13
+#define R8A7740_CLK_MMC         12
+#define R8A7740_CLK_GETHER      9
+#define R8A7740_CLK_TPU0        4
+
+/* MSTP4 */
+#define R8A7740_CLK_USBH        16
+#define R8A7740_CLK_SDHI2       15
+#define R8A7740_CLK_USBFUNC     7
+#define R8A7740_CLK_USBPHY      6
+
+/* SUBCK* */
+#define R8A7740_CLK_SUBCK       9
+#define R8A7740_CLK_SUBCK2      10
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index f929a79e6998..8ea7ab0346ad 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -26,6 +26,7 @@
 #define R8A7790_CLK_MSIOF0              0
 
 /* MSTP1 */
+#define R8A7790_CLK_JPU         6
 #define R8A7790_CLK_TMU1                11
 #define R8A7790_CLK_TMU3                21
 #define R8A7790_CLK_TMU2                22
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index f0d4d1049162..58c3f49d068c 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -25,6 +25,7 @@
 #define R8A7791_CLK_MSIOF0              0
 
 /* MSTP1 */
+#define R8A7791_CLK_JPU         6
 #define R8A7791_CLK_TMU1                11
 #define R8A7791_CLK_TMU3                21
 #define R8A7791_CLK_TMU2                22
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
new file mode 100644
index 000000000000..9ac1043e25bc
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_H__
+
+/* CPG */
+#define R8A7794_CLK_MAIN                0
+#define R8A7794_CLK_PLL0                1
+#define R8A7794_CLK_PLL1                2
+#define R8A7794_CLK_PLL3                3
+#define R8A7794_CLK_LB                  4
+#define R8A7794_CLK_QSPI                5
+#define R8A7794_CLK_SDH                 6
+#define R8A7794_CLK_SD0                 7
+#define R8A7794_CLK_Z                   8
+
+/* MSTP0 */
+#define R8A7794_CLK_MSIOF0              0
+
+/* MSTP1 */
+#define R8A7794_CLK_TMU1                11
+#define R8A7794_CLK_TMU3                21
+#define R8A7794_CLK_TMU2                22
+#define R8A7794_CLK_CMT0                24
+#define R8A7794_CLK_TMU0                25
+
+/* MSTP2 */
+#define R8A7794_CLK_SCIFA2              2
+#define R8A7794_CLK_SCIFA1              3
+#define R8A7794_CLK_SCIFA0              4
+#define R8A7794_CLK_MSIOF2              5
+#define R8A7794_CLK_SCIFB0              6
+#define R8A7794_CLK_SCIFB1              7
+#define R8A7794_CLK_MSIOF1              8
+#define R8A7794_CLK_SCIFB2              16
+
+/* MSTP3 */
+#define R8A7794_CLK_CMT1                29
+
+/* MSTP5 */
+#define R8A7794_CLK_THERMAL             22
+#define R8A7794_CLK_PWM                 23
+
+/* MSTP7 */
+#define R8A7794_CLK_HSCIF2              13
+#define R8A7794_CLK_SCIF5               14
+#define R8A7794_CLK_SCIF4               15
+#define R8A7794_CLK_HSCIF1              16
+#define R8A7794_CLK_HSCIF0              17
+#define R8A7794_CLK_SCIF3               18
+#define R8A7794_CLK_SCIF2               19
+#define R8A7794_CLK_SCIF1               20
+#define R8A7794_CLK_SCIF0               21
+
+/* MSTP8 */
+#define R8A7794_CLK_ETHER               13
+
+/* MSTP9 */
+#define R8A7794_CLK_GPIO6               5
+#define R8A7794_CLK_GPIO5               7
+#define R8A7794_CLK_GPIO4               8
+#define R8A7794_CLK_GPIO3               9
+#define R8A7794_CLK_GPIO2               10
+#define R8A7794_CLK_GPIO1               11
+#define R8A7794_CLK_GPIO0               12
+
+/* MSTP11 */
+#define R8A7794_CLK_SCIFA3              6
+#define R8A7794_CLK_SCIFA4              7
+#define R8A7794_CLK_SCIFA5              8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
index 750ee60e75fb..6a370503c954 100644
--- a/include/dt-bindings/clock/rk3188-cru-common.h
+++ b/include/dt-bindings/clock/rk3188-cru-common.h
@@ -20,6 +20,7 @@
 #define PLL_GPLL                4
 #define CORE_PERI               5
 #define CORE_L2C                6
+#define ARMCLK                  7
 
 /* sclk gates (special clocks) */
 #define SCLK_UART0              64
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index ebcb460ea4ad..100a08c47692 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -19,6 +19,7 @@
 #define PLL_CPLL                3
 #define PLL_GPLL                4
 #define PLL_NPLL                5
+#define ARMCLK                  6
 
 /* sclk gates (special clocks) */
 #define SCLK_GPU                64
@@ -61,6 +62,15 @@
 #define SCLK_LCDC_PWM1          101
 #define SCLK_MAC_RX             102
 #define SCLK_MAC_TX             103
+#define SCLK_EDP_24M            104
+#define SCLK_EDP                105
+#define SCLK_RGA                106
+#define SCLK_ISP                107
+#define SCLK_ISP_JPE            108
+#define SCLK_HDMI_HDCP          109
+#define SCLK_HDMI_CEC           110
+#define SCLK_HEVC_CABAC         111
+#define SCLK_HEVC_CORE          112
 
 #define DCLK_VOP0               190
 #define DCLK_VOP1               191
@@ -75,6 +85,16 @@
 #define ACLK_VOP1               198
 #define ACLK_CRYPTO             199
 #define ACLK_RGA                200
+#define ACLK_RGA_NIU            201
+#define ACLK_IEP                202
+#define ACLK_VIO0_NIU           203
+#define ACLK_VIP                204
+#define ACLK_ISP                205
+#define ACLK_VIO1_NIU           206
+#define ACLK_HEVC               207
+#define ACLK_VCODEC             208
+#define ACLK_CPU                209
+#define ACLK_PERI               210
 
 /* pclk gates */
 #define PCLK_GPIO0              320
@@ -112,6 +132,15 @@
 #define PCLK_PS2C               352
 #define PCLK_TIMER              353
 #define PCLK_TZPC               354
+#define PCLK_EDP_CTRL           355
+#define PCLK_MIPI_DSI0          356
+#define PCLK_MIPI_DSI1          357
+#define PCLK_MIPI_CSI           358
+#define PCLK_LVDS_PHY           359
+#define PCLK_HDMI_CTRL          360
+#define PCLK_VIO2_H2P           361
+#define PCLK_CPU                362
+#define PCLK_PERI               363
 
 /* hclk gates */
 #define HCLK_GPS                448
@@ -137,8 +166,16 @@
 #define HCLK_IEP                468
 #define HCLK_ISP                469
 #define HCLK_RGA                470
+#define HCLK_VIO_AHB_ARBI       471
+#define HCLK_VIO_NIU            472
+#define HCLK_VIP                473
+#define HCLK_VIO2_H2P           474
+#define HCLK_HEVC               475
+#define HCLK_VCODEC             476
+#define HCLK_CPU                477
+#define HCLK_PERI               478
 
-#define CLK_NR_CLKS             (HCLK_RGA + 1)
+#define CLK_NR_CLKS             (HCLK_PERI + 1)
 
 /* soft-reset indices */
 #define SRST_CORE0              0
@@ -276,3 +313,46 @@
 #define SRST_USBHOST1_CON       140
 #define SRST_USB_ADP            141
 #define SRST_ACC_EFUSE          142
+
+#define SRST_CORESIGHT          144
+#define SRST_PD_CORE_AHB_NOC    145
+#define SRST_PD_CORE_APB_NOC    146
+#define SRST_PD_CORE_MP_AXI     147
+#define SRST_GIC                148
+#define SRST_LCDC_PWM0          149
+#define SRST_LCDC_PWM1          150
+#define SRST_VIO0_H2P_BRG       151
+#define SRST_VIO1_H2P_BRG       152
+#define SRST_RGA_H2P_BRG        153
+#define SRST_HEVC               154
+#define SRST_TSADC              159
+
+#define SRST_DDRPHY0            160
+#define SRST_DDRPHY0_APB        161
+#define SRST_DDRCTRL0           162
+#define SRST_DDRCTRL0_APB       163
+#define SRST_DDRPHY0_CTRL       164
+#define SRST_DDRPHY1            165
+#define SRST_DDRPHY1_APB        166
+#define SRST_DDRCTRL1           167
+#define SRST_DDRCTRL1_APB       168
+#define SRST_DDRPHY1_CTRL       169
+#define SRST_DDRMSCH0           170
+#define SRST_DDRMSCH1           171
+#define SRST_CRYPTO             174
+#define SRST_C2C_HOST           175
+
+#define SRST_LCDC1_AXI          176
+#define SRST_LCDC1_AHB          177
+#define SRST_LCDC1_DCLK         178
+#define SRST_UART0              179
+#define SRST_UART1              180
+#define SRST_UART2              181
+#define SRST_UART3              182
+#define SRST_UART4              183
+#define SRST_SIMC               186
+#define SRST_PS2C               187
+#define SRST_TSP                188
+#define SRST_TSP_CLKIN0         189
+#define SRST_TSP_CLKIN1         190
+#define SRST_TSP_27M            191
diff --git a/include/dt-bindings/clock/rockchip,rk808.h b/include/dt-bindings/clock/rockchip,rk808.h
new file mode 100644
index 000000000000..1a873432f965
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rk808.h
@@ -0,0 +1,11 @@
+/*
+ * This header provides constants clk index RK808 pmic clkout
+ */
+#ifndef _CLK_ROCKCHIP_RK808
+#define _CLK_ROCKCHIP_RK808
+
+/* CLOCKOUT index */
+#define RK808_CLKOUT0           0
+#define RK808_CLKOUT1           1
+
+#endif
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index 8a4c5892890f..6bac637fd635 100644
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -337,6 +337,10 @@
 #define TEGRA124_CLK_DSIB_MUX 310
 #define TEGRA124_CLK_SOR0_LVDS 311
 #define TEGRA124_CLK_XUSB_SS_DIV2 312
-#define TEGRA124_CLK_CLK_MAX 313
+
+#define TEGRA124_CLK_PLL_M_UD 313
+#define TEGRA124_CLK_PLL_C_UD 314
+
+#define TEGRA124_CLK_CLK_MAX 315
 
 #endif  /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 00953d9484cb..d6b56b21539b 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -166,6 +166,9 @@
 #define VF610_CLK_DMAMUX3               153
 #define VF610_CLK_FLEXCAN0_EN           154
 #define VF610_CLK_FLEXCAN1_EN           155
-#define VF610_CLK_END                   156
+#define VF610_CLK_PLL7_MAIN             156
+#define VF610_CLK_USBPHY0               157
+#define VF610_CLK_USBPHY1               158
+#define VF610_CLK_END                   159
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/dt-bindings/input/ti-drv260x.h b/include/dt-bindings/input/ti-drv260x.h
new file mode 100644
index 000000000000..2626e6d9f707
--- /dev/null
+++ b/include/dt-bindings/input/ti-drv260x.h
@@ -0,0 +1,36 @@
+/*
+ * DRV260X haptics driver family
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * Copyright:   (C) 2014 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_TI_DRV260X_H
+#define _DT_BINDINGS_TI_DRV260X_H
+
+/* Calibration Types */
+#define DRV260X_LRA_MODE                0x00
+#define DRV260X_LRA_NO_CAL_MODE 0x01
+#define DRV260X_ERM_MODE                0x02
+
+/* Library Selection */
+#define DRV260X_LIB_EMPTY                       0x00
+#define DRV260X_ERM_LIB_A                       0x01
+#define DRV260X_ERM_LIB_B                       0x02
+#define DRV260X_ERM_LIB_C                       0x03
+#define DRV260X_ERM_LIB_D                       0x04
+#define DRV260X_ERM_LIB_E                       0x05
+#define DRV260X_LIB_LRA                 0x06
+#define DRV260X_ERM_LIB_F                       0x07
+
+#endif
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
index 0fee6ff77ffc..bbca3d038900 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -20,6 +20,11 @@
 
 #define AT91_PINCTRL_PULL_UP_DEGLITCH   (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
 
+#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT             (0x0 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_LOW                 (0x1 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_MED                 (0x2 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_HI                  (0x3 << 5)
+
 #define AT91_PIOA       0
 #define AT91_PIOB       1
 #define AT91_PIOC       2
diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h
index cd5788be82ce..743e66a95e13 100644
--- a/include/dt-bindings/pinctrl/rockchip.h
+++ b/include/dt-bindings/pinctrl/rockchip.h
@@ -28,5 +28,7 @@
 #define RK_FUNC_GPIO    0
 #define RK_FUNC_1       1
 #define RK_FUNC_2       2
+#define RK_FUNC_3       3
+#define RK_FUNC_4       4
 
 #endif