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| author | Mike Turquette <mturquette@linaro.org> | 2014-07-02 13:05:56 -0400 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-07-02 13:05:56 -0400 |
| commit | 4924b8a2fa137335bef82829733b30a5172e51b3 (patch) | |
| tree | b4475934e16fb14f1413f2a2892c732af420b1f4 /include/dt-bindings | |
| parent | 5c726dcdd22d2fa007a87e258128393acfc364d2 (diff) | |
| parent | 44ff0254b89079a8a95e652635e760d93196ac1f (diff) | |
Merge tag 'for_3.16/samsung-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-fixes-samsung
Samsung clock fixes for v3.16.
This pull request contains fixes for various issues found while testing
-rc versions of Linux 3.16. Mostly two kinds of patches:
* Fixes of incorrectly defined clocks
1) a37c82a clk: samsung: exynos4: Remove SRC_MASK_ISP gates
Issue present since v3.10.
2) 0b1643b clk/exynos5250: fix bit number for tv sysmmu clock
Issue present since v3.16.
3) 44ff025 clk: exynos5420: Remove aclk66_peric from the clock tree description
Issue present since v3.11.
* Adding things missed by original patches
1) cec1cde clk: samsung: fix several typos to fix boot on s3c2410
2) 34ece9e clk: samsung: add more aliases for s3c24xx
Both issues present since the driver was added in v3.16.
3) a92dda4 clk: s3c64xx: Hookup SPI clocks correctly
Issue present since v3.12.
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/exynos5420.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 97dcb89d37d3..14e1c8f9640c 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h | |||
| @@ -63,7 +63,6 @@ | |||
| 63 | #define CLK_SCLK_MPHY_IXTAL24 161 | 63 | #define CLK_SCLK_MPHY_IXTAL24 161 |
| 64 | 64 | ||
| 65 | /* gate clocks */ | 65 | /* gate clocks */ |
| 66 | #define CLK_ACLK66_PERIC 256 | ||
| 67 | #define CLK_UART0 257 | 66 | #define CLK_UART0 257 |
| 68 | #define CLK_UART1 258 | 67 | #define CLK_UART1 258 |
| 69 | #define CLK_UART2 259 | 68 | #define CLK_UART2 259 |