clk: samsung: exynos5433: Add clocks for CMU_CAM1 domain

This patch adds the mux/divider/gate clocks for CMU_CAM1 domain which
generates the clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

1 files changed, 145 insertions, 2 deletions

diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index f99cde7a278d..4853bc598b57 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -121,6 +121,20 @@
 #define CLK_DIV_ACLK_CAM0_333           148
 #define CLK_DIV_ACLK_CAM0_400           149
 #define CLK_DIV_ACLK_CAM0_552           150
+#define CLK_DIV_ACLK_CAM1_333           151
+#define CLK_DIV_ACLK_CAM1_400           152
+#define CLK_DIV_ACLK_CAM1_552           153
+#define CLK_DIV_SCLK_ISP_UART           154
+#define CLK_DIV_SCLK_ISP_SPI1_B         155
+#define CLK_DIV_SCLK_ISP_SPI1_A         156
+#define CLK_DIV_SCLK_ISP_SPI0_B         157
+#define CLK_DIV_SCLK_ISP_SPI0_A         158
+#define CLK_DIV_SCLK_ISP_SENSOR2_B      159
+#define CLK_DIV_SCLK_ISP_SENSOR2_A      160
+#define CLK_DIV_SCLK_ISP_SENSOR1_B      161
+#define CLK_DIV_SCLK_ISP_SENSOR1_A      162
+#define CLK_DIV_SCLK_ISP_SENSOR0_B      163
+#define CLK_DIV_SCLK_ISP_SENSOR0_A      164
 
 #define CLK_ACLK_PERIC_66               200
 #define CLK_ACLK_PERIS_66               201
@@ -165,8 +179,18 @@
 #define CLK_ACLK_CAM0_333               240
 #define CLK_ACLK_CAM0_400               241
 #define CLK_ACLK_CAM0_552               242
-
-#define TOP_NR_CLK                      243
+#define CLK_ACLK_CAM1_333               243
+#define CLK_ACLK_CAM1_400               244
+#define CLK_ACLK_CAM1_552               245
+#define CLK_SCLK_ISP_SENSOR2            246
+#define CLK_SCLK_ISP_SENSOR1            247
+#define CLK_SCLK_ISP_SENSOR0            248
+#define CLK_SCLK_ISP_MCTADC_CAM1        249
+#define CLK_SCLK_ISP_UART_CAM1          250
+#define CLK_SCLK_ISP_SPI1_CAM1          251
+#define CLK_SCLK_ISP_SPI0_CAM1          252
+
+#define TOP_NR_CLK                      253
 
 /* CMU_CPIF */
 #define CLK_FOUT_MPHY_PLL               1
@@ -1257,4 +1281,123 @@
 
 #define CAM0_NR_CLK                                     134
 
+/* CMU_CAM1 */
+#define CLK_PHYCLK_RXBYTEECLKHS0_S2B                    1
+
+#define CLK_MOUT_SCLK_ISP_UART_USER                     2
+#define CLK_MOUT_SCLK_ISP_SPI1_USER                     3
+#define CLK_MOUT_SCLK_ISP_SPI0_USER                     4
+#define CLK_MOUT_ACLK_CAM1_333_USER                     5
+#define CLK_MOUT_ACLK_CAM1_400_USER                     6
+#define CLK_MOUT_ACLK_CAM1_552_USER                     7
+#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER           8
+#define CLK_MOUT_ACLK_CSIS2_B                           9
+#define CLK_MOUT_ACLK_CSIS2_A                           10
+#define CLK_MOUT_ACLK_FD_B                              11
+#define CLK_MOUT_ACLK_FD_A                              12
+#define CLK_MOUT_ACLK_LITE_C_B                          13
+#define CLK_MOUT_ACLK_LITE_C_A                          14
+
+#define CLK_DIV_SCLK_ISP_WPWM                           15
+#define CLK_DIV_PCLK_CAM1_83                            16
+#define CLK_DIV_PCLK_CAM1_166                           17
+#define CLK_DIV_PCLK_DBG_CAM1                           18
+#define CLK_DIV_ATCLK_CAM1                              19
+#define CLK_DIV_ACLK_CSIS2                              20
+#define CLK_DIV_PCLK_FD                                 21
+#define CLK_DIV_ACLK_FD                                 22
+#define CLK_DIV_PCLK_LITE_C                             23
+#define CLK_DIV_ACLK_LITE_C                             24
+
+#define CLK_ACLK_ISP_GIC                                25
+#define CLK_ACLK_FD                                     26
+#define CLK_ACLK_LITE_C                                 27
+#define CLK_ACLK_CSIS2                                  28
+#define CLK_ACLK_ASYNCAPBM_FD                           29
+#define CLK_ACLK_ASYNCAPBS_FD                           30
+#define CLK_ACLK_ASYNCAPBM_LITE_C                       31
+#define CLK_ACLK_ASYNCAPBS_LITE_C                       32
+#define CLK_ACLK_ASYNCAHBS_SFRISP2H2                    33
+#define CLK_ACLK_ASYNCAHBS_SFRISP2H1                    34
+#define CLK_ACLK_ASYNCAXIM_CA5                          35
+#define CLK_ACLK_ASYNCAXIS_CA5                          36
+#define CLK_ACLK_ASYNCAXIS_ISPX2                        37
+#define CLK_ACLK_ASYNCAXIS_ISPX1                        38
+#define CLK_ACLK_ASYNCAXIS_ISPX0                        39
+#define CLK_ACLK_ASYNCAXIM_ISPEX                        40
+#define CLK_ACLK_ASYNCAXIM_ISP3P                        41
+#define CLK_ACLK_ASYNCAXIS_ISP3P                        42
+#define CLK_ACLK_ASYNCAXIM_FD                           43
+#define CLK_ACLK_ASYNCAXIS_FD                           44
+#define CLK_ACLK_ASYNCAXIM_LITE_C                       45
+#define CLK_ACLK_ASYNCAXIS_LITE_C                       46
+#define CLK_ACLK_AHB2APB_ISP5P                          47
+#define CLK_ACLK_AHB2APB_ISP3P                          48
+#define CLK_ACLK_AXI2APB_ISP3P                          49
+#define CLK_ACLK_AHB_SFRISP2H                           50
+#define CLK_ACLK_AXI_ISP_HX_R                           51
+#define CLK_ACLK_AXI_ISP_CX_R                           52
+#define CLK_ACLK_AXI_ISP_HX                             53
+#define CLK_ACLK_AXI_ISP_CX                             54
+#define CLK_ACLK_XIU_ISPX                               55
+#define CLK_ACLK_XIU_ISPEX                              56
+#define CLK_ACLK_CAM1NP_333                             57
+#define CLK_ACLK_CAM1ND_400                             58
+#define CLK_ACLK_SMMU_ISPCPU                            59
+#define CLK_ACLK_SMMU_FD                                60
+#define CLK_ACLK_SMMU_LITE_C                            61
+#define CLK_ACLK_BTS_ISP3P                              62
+#define CLK_ACLK_BTS_FD                                 63
+#define CLK_ACLK_BTS_LITE_C                             64
+#define CLK_ACLK_AHBDN_SFRISP2H                         65
+#define CLK_ACLK_AHBDN_ISP5P                            66
+#define CLK_ACLK_AXIUS_ISP3P                            67
+#define CLK_ACLK_AXIUS_FD                               68
+#define CLK_ACLK_AXIUS_LITE_C                           69
+#define CLK_PCLK_SMMU_ISPCPU                            70
+#define CLK_PCLK_SMMU_FD                                71
+#define CLK_PCLK_SMMU_LITE_C                            72
+#define CLK_PCLK_BTS_ISP3P                              73
+#define CLK_PCLK_BTS_FD                                 74
+#define CLK_PCLK_BTS_LITE_C                             75
+#define CLK_PCLK_ASYNCAXIM_CA5                          76
+#define CLK_PCLK_ASYNCAXIM_ISPEX                        77
+#define CLK_PCLK_ASYNCAXIM_ISP3P                        78
+#define CLK_PCLK_ASYNCAXIM_FD                           79
+#define CLK_PCLK_ASYNCAXIM_LITE_C                       80
+#define CLK_PCLK_PMU_CAM1                               81
+#define CLK_PCLK_SYSREG_CAM1                            82
+#define CLK_PCLK_CMU_CAM1_LOCAL                         83
+#define CLK_PCLK_ISP_MCTADC                             84
+#define CLK_PCLK_ISP_WDT                                85
+#define CLK_PCLK_ISP_PWM                                86
+#define CLK_PCLK_ISP_UART                               87
+#define CLK_PCLK_ISP_MCUCTL                             88
+#define CLK_PCLK_ISP_SPI1                               89
+#define CLK_PCLK_ISP_SPI0                               90
+#define CLK_PCLK_ISP_I2C2                               91
+#define CLK_PCLK_ISP_I2C1                               92
+#define CLK_PCLK_ISP_I2C0                               93
+#define CLK_PCLK_ISP_MPWM                               94
+#define CLK_PCLK_FD                                     95
+#define CLK_PCLK_LITE_C                                 96
+#define CLK_PCLK_CSIS2                                  97
+#define CLK_SCLK_ISP_I2C2                               98
+#define CLK_SCLK_ISP_I2C1                               99
+#define CLK_SCLK_ISP_I2C0                               100
+#define CLK_SCLK_ISP_PWM                                101
+#define CLK_PHYCLK_RXBYTECLKHS0_S2B                     102
+#define CLK_SCLK_LITE_C_FREECNT                         103
+#define CLK_SCLK_PIXELASYNCM_FD                         104
+#define CLK_SCLK_ISP_MCTADC                             105
+#define CLK_SCLK_ISP_UART                               106
+#define CLK_SCLK_ISP_SPI1                               107
+#define CLK_SCLK_ISP_SPI0                               108
+#define CLK_SCLK_ISP_MPWM                               109
+#define CLK_PCLK_DBG_ISP                                110
+#define CLK_ATCLK_ISP                                   111
+#define CLK_SCLK_ISP_CA5                                112
+
+#define CAM1_NR_CLK                                     113
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */