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authorOlof Johansson <olof@lixom.net>2015-02-06 03:03:28 -0500
committerOlof Johansson <olof@lixom.net>2015-02-06 03:03:28 -0500
commit6f8c8f6baf919da1804291f3abd9414c3f71b838 (patch)
tree5396b71346659a174f7e8c050d3edad11140d9b1 /include/dt-bindings/clock
parent7679f31f143bb3b770b80855af254bb6ee0a1f89 (diff)
parentc25d8cbcd840b2c9774a285ea728e72dd56aea2e (diff)
Merge tag 'v3.20-rockchip-dts3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Merge "ARM: rockchip: third (and last) batch of dts updates for 3.20" from Heiko Stübner: Change are regulator nodes for the cpu and gpu regulators on the act8846 variant of the rk3288-evb and the setting of a clock for the watchdog. Also the lcd and hdmi controllers on both the firefly and the evb get enabled and let us now boot into fbcon console sucessfully. * tag 'v3.20-rockchip-dts3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb ARM: dts: rockchip: housekeeping off i2c0 on rk3288-evb boards ARM: dts: rockchip: add cpu and gpu regulators to rk3288-evb-act8846 ARM: dts: rockchip: add rk3288 watchdog clock clk: rockchip: add id for watchdog pclk on rk3288 clk: rockchip: add clock IDs for the PVTM clocks clk: rockchip: add clock ID for usbphy480m_src Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include/dt-bindings/clock')
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index f60ce72a2b2c..1e626335acf3 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -80,6 +80,9 @@
80#define SCLK_SDIO0_SAMPLE 119 80#define SCLK_SDIO0_SAMPLE 119
81#define SCLK_SDIO1_SAMPLE 120 81#define SCLK_SDIO1_SAMPLE 120
82#define SCLK_EMMC_SAMPLE 121 82#define SCLK_EMMC_SAMPLE 121
83#define SCLK_USBPHY480M_SRC 122
84#define SCLK_PVTM_CORE 123
85#define SCLK_PVTM_GPU 124
83 86
84#define DCLK_VOP0 190 87#define DCLK_VOP0 190
85#define DCLK_VOP1 191 88#define DCLK_VOP1 191
@@ -154,6 +157,7 @@
154#define PCLK_PUBL0 365 157#define PCLK_PUBL0 365
155#define PCLK_DDRUPCTL1 366 158#define PCLK_DDRUPCTL1 366
156#define PCLK_PUBL1 367 159#define PCLK_PUBL1 367
160#define PCLK_WDT 368
157 161
158/* hclk gates */ 162/* hclk gates */
159#define HCLK_GPS 448 163#define HCLK_GPS 448