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authorIngo Molnar <mingo@kernel.org>2014-07-16 09:10:07 -0400
committerIngo Molnar <mingo@kernel.org>2014-07-16 09:10:07 -0400
commitd26fad5b38e1c4667d4f2604936e59c837caa54d (patch)
tree04b524a69a0129c181567445bff18847a1b44721 /include/dt-bindings/clock/exynos5420.h
parente720fff6341fe4b95e5a93c939bd3c77fa55ced4 (diff)
parent1795cd9b3a91d4b5473c97f491d63892442212ab (diff)
Merge tag 'v3.16-rc5' into sched/core, to refresh the branch before applying bigger tree-wide changes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'include/dt-bindings/clock/exynos5420.h')
-rw-r--r--include/dt-bindings/clock/exynos5420.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 97dcb89d37d3..21d51ae1d242 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -63,7 +63,6 @@
63#define CLK_SCLK_MPHY_IXTAL24 161 63#define CLK_SCLK_MPHY_IXTAL24 161
64 64
65/* gate clocks */ 65/* gate clocks */
66#define CLK_ACLK66_PERIC 256
67#define CLK_UART0 257 66#define CLK_UART0 257
68#define CLK_UART1 258 67#define CLK_UART1 258
69#define CLK_UART2 259 68#define CLK_UART2 259
@@ -203,6 +202,8 @@
203#define CLK_MOUT_G3D 641 202#define CLK_MOUT_G3D 641
204#define CLK_MOUT_VPLL 642 203#define CLK_MOUT_VPLL 642
205#define CLK_MOUT_MAUDIO0 643 204#define CLK_MOUT_MAUDIO0 643
205#define CLK_MOUT_USER_ACLK333 644
206#define CLK_MOUT_SW_ACLK333 645
206 207
207/* divider clocks */ 208/* divider clocks */
208#define CLK_DOUT_PIXEL 768 209#define CLK_DOUT_PIXEL 768