drm/radeon: add support for evergreen/ni tiling informations v11

evergreen and northern island gpu needs more informations for 2D tiling
than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace
to provide those.

The v8 cs checking change to track color view on r6xx/r7xx doesn't
affect old userspace as old userspace always emited 0 for this register.

v2 fix r6xx/r7xx 2D tiling computation
v3 fix r6xx/r7xx height align for untiled surface & add support for
   tile split on evergreen and newer
v4 improve tiling debugging output
v5 fix tile split code for evergreen and newer
v6 set proper tile split for crtc register
v7 fix tile split limit value
v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs
   checking, update safe reg for r600, evergreen and cayman.
   Evergreen checking need some work around for stencil alignment
   issues
v9 fix tile split value range, fix compressed texture handling and
   mipmap calculation, allow evergreen check to be silencious in
   front of current broken userspace (depth/stencil alignment issue)
v10 fix eg 3d texture and compressed texture, fix r600 depth array,
    fix r600 color view computation, add support for evergreen stencil
    split
v11 more verbose debugging in some case

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 17 insertions, 7 deletions

diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index b55da40953fd..cb2f0c362a13 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -804,13 +804,23 @@ struct drm_radeon_gem_create {
         uint32_t        flags;
 };
 
-#define RADEON_TILING_MACRO       0x1
-#define RADEON_TILING_MICRO       0x2
-#define RADEON_TILING_SWAP_16BIT  0x4
-#define RADEON_TILING_SWAP_32BIT  0x8
-#define RADEON_TILING_SURFACE     0x10 /* this object requires a surface
-                                        * when mapped - i.e. front buffer */
-#define RADEON_TILING_MICRO_SQUARE 0x20
+#define RADEON_TILING_MACRO                             0x1
+#define RADEON_TILING_MICRO                             0x2
+#define RADEON_TILING_SWAP_16BIT                        0x4
+#define RADEON_TILING_SWAP_32BIT                        0x8
+/* this object requires a surface when mapped - i.e. front buffer */
+#define RADEON_TILING_SURFACE                           0x10
+#define RADEON_TILING_MICRO_SQUARE                      0x20
+#define RADEON_TILING_EG_BANKW_SHIFT                    8
+#define RADEON_TILING_EG_BANKW_MASK                     0xf
+#define RADEON_TILING_EG_BANKH_SHIFT                    12
+#define RADEON_TILING_EG_BANKH_MASK                     0xf
+#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT        16
+#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK         0xf
+#define RADEON_TILING_EG_TILE_SPLIT_SHIFT               24
+#define RADEON_TILING_EG_TILE_SPLIT_MASK                0xf
+#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT       28
+#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK        0xf
 
 struct drm_radeon_gem_set_tiling {
         uint32_t        handle;