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authorDave Airlie <airlied@redhat.com>2015-04-15 18:33:30 -0400
committerDave Airlie <airlied@redhat.com>2015-04-15 18:33:30 -0400
commit52139bdea1558e854123d7a07e7648f5a8c77a5c (patch)
tree846c411449c8a4f0618ec3426cff697428cc0c51 /include/drm
parentfc16fc4d69d5f1b67d3d6ac97bd3b4e1cc3f74cc (diff)
parent1dbee1a3c38a8792c235048df1d709fc5ca3a185 (diff)
Merge branch 'drm-dwhdmi-devel' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into drm-next
This set of patches adjust the setup of the HDMI CTS/N values for audio support to be compliant with the work-around given in the iMX6 errata documentation as part of the preparation for integrating audio support for this driver, and also update the HDMI phy configuration for Rockchip devices to improve the HDMI eye pattern. * 'drm-dwhdmi-devel' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: drm: rockchip/dw_hdmi-rockchip: improve for HDMI electrical test drm: bridge/dw_hdmi: separate VLEVCTRL settting into platform driver drm: bridge/dw_hdmi: fixed codec style drm: bridge/dw_hdmi: adjust n/cts setting order drm: bridge/dw_hdmi: protect n/cts setting with a mutex drm: bridge/dw_hdmi: combine hdmi_set_clock_regenerator_n() and hdmi_regenerate_cts() Conflicts: drivers/gpu/drm/imx/dw_hdmi-imx.c
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/bridge/dw_hdmi.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 5a4f49005169..de13bfc35634 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -38,17 +38,18 @@ struct dw_hdmi_curr_ctrl {
38 u16 curr[DW_HDMI_RES_MAX]; 38 u16 curr[DW_HDMI_RES_MAX];
39}; 39};
40 40
41struct dw_hdmi_sym_term { 41struct dw_hdmi_phy_config {
42 unsigned long mpixelclock; 42 unsigned long mpixelclock;
43 u16 sym_ctr; /*clock symbol and transmitter control*/ 43 u16 sym_ctr; /*clock symbol and transmitter control*/
44 u16 term; /*transmission termination value*/ 44 u16 term; /*transmission termination value*/
45 u16 vlev_ctr; /* voltage level control */
45}; 46};
46 47
47struct dw_hdmi_plat_data { 48struct dw_hdmi_plat_data {
48 enum dw_hdmi_devtype dev_type; 49 enum dw_hdmi_devtype dev_type;
49 const struct dw_hdmi_mpll_config *mpll_cfg; 50 const struct dw_hdmi_mpll_config *mpll_cfg;
50 const struct dw_hdmi_curr_ctrl *cur_ctr; 51 const struct dw_hdmi_curr_ctrl *cur_ctr;
51 const struct dw_hdmi_sym_term *sym_term; 52 const struct dw_hdmi_phy_config *phy_config;
52 enum drm_mode_status (*mode_valid)(struct drm_connector *connector, 53 enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
53 struct drm_display_mode *mode); 54 struct drm_display_mode *mode);
54}; 55};