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authorChris Wilson <chris@chris-wilson.co.uk>2010-09-24 16:15:47 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-10-29 06:15:07 -0400
commita00b10c360b35d6431a94cbf130a4e162870d661 (patch)
treee1c06b90d161bc81e8d2c819da3b676f75527dda /include/drm
parent7465378fd7c681f6cf2b74b3494c4f0991d8c8ac (diff)
drm/i915: Only enforce fence limits inside the GTT.
So long as we adhere to the fence registers rules for alignment and no overlaps (including with unfenced accesses to linear memory) and account for the tiled access in our size allocation, we do not have to allocate the full fenced region for the object. This allows us to fight the bloat tiling imposed on pre-i965 chipsets and frees up RAM for real use. [Inside the GTT we still suffer the additional alignment constraints, so it doesn't magic allow us to render larger scenes without stalls -- we need the expanded GTT and fence pipelining to overcome those...] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/i915_drm.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 8c641bed9bbd..b20dbb2d7174 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -287,6 +287,7 @@ typedef struct drm_i915_irq_wait {
287#define I915_PARAM_HAS_EXECBUF2 9 287#define I915_PARAM_HAS_EXECBUF2 9
288#define I915_PARAM_HAS_BSD 10 288#define I915_PARAM_HAS_BSD 10
289#define I915_PARAM_HAS_BLT 11 289#define I915_PARAM_HAS_BLT 11
290#define I915_PARAM_HAS_RELAXED_FENCING 12
290 291
291typedef struct drm_i915_getparam { 292typedef struct drm_i915_getparam {
292 int param; 293 int param;