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authorBen Skeggs <bskeggs@redhat.com>2010-02-11 19:27:35 -0500
committerBen Skeggs <bskeggs@redhat.com>2010-02-25 00:08:44 -0500
commita1606a9596e54da90ad6209071b357a4c1b0fa82 (patch)
tree1f01726a80ea1e374d87fb6c6ebe3bbc6015b36a /include/drm
parentd87897d4c853a5c136f60efa858d0d4cb3740f57 (diff)
drm/nouveau: new gem pushbuf interface, bump to 0.0.16
This commit breaks the userspace interface, and requires a new libdrm for nouveau to operate again. The multiple GEM_PUSHBUF ioctls that were present in 0.0.15 for compatibility purposes are now gone, and replaced with the new ioctl which allows for multiple push buffers to be submitted (necessary for hw index buffers in the nv50 3d driver) and relocations to be applied on any buffer. A number of other ioctls (CARD_INIT, GEM_PIN, GEM_UNPIN) that were needed for userspace modesetting have also been removed. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/nouveau_drm.h86
1 files changed, 32 insertions, 54 deletions
diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
index f745948b61e4..a6a9f4af5ebd 100644
--- a/include/drm/nouveau_drm.h
+++ b/include/drm/nouveau_drm.h
@@ -25,13 +25,14 @@
25#ifndef __NOUVEAU_DRM_H__ 25#ifndef __NOUVEAU_DRM_H__
26#define __NOUVEAU_DRM_H__ 26#define __NOUVEAU_DRM_H__
27 27
28#define NOUVEAU_DRM_HEADER_PATCHLEVEL 15 28#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
29 29
30struct drm_nouveau_channel_alloc { 30struct drm_nouveau_channel_alloc {
31 uint32_t fb_ctxdma_handle; 31 uint32_t fb_ctxdma_handle;
32 uint32_t tt_ctxdma_handle; 32 uint32_t tt_ctxdma_handle;
33 33
34 int channel; 34 int channel;
35 uint32_t pushbuf_domains;
35 36
36 /* Notifier memory */ 37 /* Notifier memory */
37 uint32_t notifier_handle; 38 uint32_t notifier_handle;
@@ -109,68 +110,58 @@ struct drm_nouveau_gem_new {
109 uint32_t align; 110 uint32_t align;
110}; 111};
111 112
113#define NOUVEAU_GEM_MAX_BUFFERS 1024
114struct drm_nouveau_gem_pushbuf_bo_presumed {
115 uint32_t valid;
116 uint32_t domain;
117 uint64_t offset;
118};
119
112struct drm_nouveau_gem_pushbuf_bo { 120struct drm_nouveau_gem_pushbuf_bo {
113 uint64_t user_priv; 121 uint64_t user_priv;
114 uint32_t handle; 122 uint32_t handle;
115 uint32_t read_domains; 123 uint32_t read_domains;
116 uint32_t write_domains; 124 uint32_t write_domains;
117 uint32_t valid_domains; 125 uint32_t valid_domains;
118 uint32_t presumed_ok; 126 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
119 uint32_t presumed_domain;
120 uint64_t presumed_offset;
121}; 127};
122 128
123#define NOUVEAU_GEM_RELOC_LOW (1 << 0) 129#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
124#define NOUVEAU_GEM_RELOC_HIGH (1 << 1) 130#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
125#define NOUVEAU_GEM_RELOC_OR (1 << 2) 131#define NOUVEAU_GEM_RELOC_OR (1 << 2)
132#define NOUVEAU_GEM_MAX_RELOCS 1024
126struct drm_nouveau_gem_pushbuf_reloc { 133struct drm_nouveau_gem_pushbuf_reloc {
134 uint32_t reloc_bo_index;
135 uint32_t reloc_bo_offset;
127 uint32_t bo_index; 136 uint32_t bo_index;
128 uint32_t reloc_index;
129 uint32_t flags; 137 uint32_t flags;
130 uint32_t data; 138 uint32_t data;
131 uint32_t vor; 139 uint32_t vor;
132 uint32_t tor; 140 uint32_t tor;
133}; 141};
134 142
135#define NOUVEAU_GEM_MAX_BUFFERS 1024 143#define NOUVEAU_GEM_MAX_PUSH 512
136#define NOUVEAU_GEM_MAX_RELOCS 1024 144struct drm_nouveau_gem_pushbuf_push {
145 uint32_t bo_index;
146 uint32_t pad;
147 uint64_t offset;
148 uint64_t length;
149};
137 150
138struct drm_nouveau_gem_pushbuf { 151struct drm_nouveau_gem_pushbuf {
139 uint32_t channel; 152 uint32_t channel;
140 uint32_t nr_dwords;
141 uint32_t nr_buffers; 153 uint32_t nr_buffers;
142 uint32_t nr_relocs;
143 uint64_t dwords;
144 uint64_t buffers; 154 uint64_t buffers;
145 uint64_t relocs;
146};
147
148struct drm_nouveau_gem_pushbuf_call {
149 uint32_t channel;
150 uint32_t handle;
151 uint32_t offset;
152 uint32_t nr_buffers;
153 uint32_t nr_relocs; 155 uint32_t nr_relocs;
154 uint32_t nr_dwords; 156 uint32_t nr_push;
155 uint64_t buffers;
156 uint64_t relocs; 157 uint64_t relocs;
158 uint64_t push;
157 uint32_t suffix0; 159 uint32_t suffix0;
158 uint32_t suffix1; 160 uint32_t suffix1;
159 /* below only accessed for CALL2 */
160 uint64_t vram_available; 161 uint64_t vram_available;
161 uint64_t gart_available; 162 uint64_t gart_available;
162}; 163};
163 164
164struct drm_nouveau_gem_pin {
165 uint32_t handle;
166 uint32_t domain;
167 uint64_t offset;
168};
169
170struct drm_nouveau_gem_unpin {
171 uint32_t handle;
172};
173
174#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 165#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
175#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 166#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
176#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 167#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
@@ -183,14 +174,6 @@ struct drm_nouveau_gem_cpu_fini {
183 uint32_t handle; 174 uint32_t handle;
184}; 175};
185 176
186struct drm_nouveau_gem_tile {
187 uint32_t handle;
188 uint32_t offset;
189 uint32_t size;
190 uint32_t tile_mode;
191 uint32_t tile_flags;
192};
193
194enum nouveau_bus_type { 177enum nouveau_bus_type {
195 NV_AGP = 0, 178 NV_AGP = 0,
196 NV_PCI = 1, 179 NV_PCI = 1,
@@ -200,22 +183,17 @@ enum nouveau_bus_type {
200struct drm_nouveau_sarea { 183struct drm_nouveau_sarea {
201}; 184};
202 185
203#define DRM_NOUVEAU_CARD_INIT 0x00 186#define DRM_NOUVEAU_GETPARAM 0x00
204#define DRM_NOUVEAU_GETPARAM 0x01 187#define DRM_NOUVEAU_SETPARAM 0x01
205#define DRM_NOUVEAU_SETPARAM 0x02 188#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
206#define DRM_NOUVEAU_CHANNEL_ALLOC 0x03 189#define DRM_NOUVEAU_CHANNEL_FREE 0x03
207#define DRM_NOUVEAU_CHANNEL_FREE 0x04 190#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
208#define DRM_NOUVEAU_GROBJ_ALLOC 0x05 191#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
209#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06 192#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
210#define DRM_NOUVEAU_GPUOBJ_FREE 0x07
211#define DRM_NOUVEAU_GEM_NEW 0x40 193#define DRM_NOUVEAU_GEM_NEW 0x40
212#define DRM_NOUVEAU_GEM_PUSHBUF 0x41 194#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
213#define DRM_NOUVEAU_GEM_PUSHBUF_CALL 0x42 195#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
214#define DRM_NOUVEAU_GEM_PIN 0x43 /* !KMS only */ 196#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
215#define DRM_NOUVEAU_GEM_UNPIN 0x44 /* !KMS only */ 197#define DRM_NOUVEAU_GEM_INFO 0x44
216#define DRM_NOUVEAU_GEM_CPU_PREP 0x45
217#define DRM_NOUVEAU_GEM_CPU_FINI 0x46
218#define DRM_NOUVEAU_GEM_INFO 0x47
219#define DRM_NOUVEAU_GEM_PUSHBUF_CALL2 0x48
220 198
221#endif /* __NOUVEAU_DRM_H__ */ 199#endif /* __NOUVEAU_DRM_H__ */