diff options
author | Marek Olšák <maraeo@gmail.com> | 2011-08-07 16:39:04 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2011-08-31 14:25:48 -0400 |
commit | d3ed74027f1dd197b7e08247a40d3bf9be1852b0 (patch) | |
tree | 9d4fbd62d8fb5d505c1b934f13bccb762ab47dff /include/drm | |
parent | dfadbbdb57b3f2bb33e14f129a43047c6f0caefa (diff) |
drm/radeon/kms: add a new gem_wait ioctl with read/write flags
The new DRM_RADEON_GEM_WAIT ioctl combines GEM_WAIT_IDLE and GEM_BUSY (there
is a NO_WAIT flag to get the latter) with USAGE_READ and USAGE_WRITE flags
to take advantage of the new ttm_bo_wait changes.
Also bump the DRM version.
Signed-off-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'include/drm')
-rw-r--r-- | include/drm/radeon_drm.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h index b65be6054a18..939b8547cc26 100644 --- a/include/drm/radeon_drm.h +++ b/include/drm/radeon_drm.h | |||
@@ -509,6 +509,7 @@ typedef struct { | |||
509 | #define DRM_RADEON_GEM_SET_TILING 0x28 | 509 | #define DRM_RADEON_GEM_SET_TILING 0x28 |
510 | #define DRM_RADEON_GEM_GET_TILING 0x29 | 510 | #define DRM_RADEON_GEM_GET_TILING 0x29 |
511 | #define DRM_RADEON_GEM_BUSY 0x2a | 511 | #define DRM_RADEON_GEM_BUSY 0x2a |
512 | #define DRM_RADEON_GEM_WAIT 0x2b | ||
512 | 513 | ||
513 | #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) | 514 | #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) |
514 | #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) | 515 | #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) |
@@ -550,6 +551,7 @@ typedef struct { | |||
550 | #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) | 551 | #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) |
551 | #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) | 552 | #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) |
552 | #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) | 553 | #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) |
554 | #define DRM_IOCTL_RADEON_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT, struct drm_radeon_gem_wait) | ||
553 | 555 | ||
554 | typedef struct drm_radeon_init { | 556 | typedef struct drm_radeon_init { |
555 | enum { | 557 | enum { |
@@ -846,6 +848,15 @@ struct drm_radeon_gem_busy { | |||
846 | uint32_t domain; | 848 | uint32_t domain; |
847 | }; | 849 | }; |
848 | 850 | ||
851 | #define RADEON_GEM_NO_WAIT 0x1 | ||
852 | #define RADEON_GEM_USAGE_READ 0x2 | ||
853 | #define RADEON_GEM_USAGE_WRITE 0x4 | ||
854 | |||
855 | struct drm_radeon_gem_wait { | ||
856 | uint32_t handle; | ||
857 | uint32_t flags; /* one of RADEON_GEM_* */ | ||
858 | }; | ||
859 | |||
849 | struct drm_radeon_gem_pread { | 860 | struct drm_radeon_gem_pread { |
850 | /** Handle for the object being read. */ | 861 | /** Handle for the object being read. */ |
851 | uint32_t handle; | 862 | uint32_t handle; |