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authorBen Skeggs <bskeggs@redhat.com>2012-05-07 20:24:27 -0400
committerBen Skeggs <bskeggs@redhat.com>2012-07-25 20:28:15 -0400
commit2a259a3d84c4409918c5d094f0969da58283a947 (patch)
treee261df7f7f038bbb9761c91ee5784a4fdfb0bfb5 /include/drm
parentce22af03da2cd700332a384e240378cae1355773 (diff)
drm/nouveau: mark most of our ioctls as deprecated, move to compat layer
These will be replaced in the near future, the code isn't yet stable enough for this merge window however. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/nouveau_drm.h94
1 files changed, 7 insertions, 87 deletions
diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
index 5edd3a76fffa..2a5769fdf8ba 100644
--- a/include/drm/nouveau_drm.h
+++ b/include/drm/nouveau_drm.h
@@ -25,70 +25,6 @@
25#ifndef __NOUVEAU_DRM_H__ 25#ifndef __NOUVEAU_DRM_H__
26#define __NOUVEAU_DRM_H__ 26#define __NOUVEAU_DRM_H__
27 27
28#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
29
30struct drm_nouveau_channel_alloc {
31 uint32_t fb_ctxdma_handle;
32 uint32_t tt_ctxdma_handle;
33
34 int channel;
35 uint32_t pushbuf_domains;
36
37 /* Notifier memory */
38 uint32_t notifier_handle;
39
40 /* DRM-enforced subchannel assignments */
41 struct {
42 uint32_t handle;
43 uint32_t grclass;
44 } subchan[8];
45 uint32_t nr_subchan;
46};
47
48struct drm_nouveau_channel_free {
49 int channel;
50};
51
52struct drm_nouveau_grobj_alloc {
53 int channel;
54 uint32_t handle;
55 int class;
56};
57
58struct drm_nouveau_notifierobj_alloc {
59 uint32_t channel;
60 uint32_t handle;
61 uint32_t size;
62 uint32_t offset;
63};
64
65struct drm_nouveau_gpuobj_free {
66 int channel;
67 uint32_t handle;
68};
69
70/* FIXME : maybe unify {GET,SET}PARAMs */
71#define NOUVEAU_GETPARAM_PCI_VENDOR 3
72#define NOUVEAU_GETPARAM_PCI_DEVICE 4
73#define NOUVEAU_GETPARAM_BUS_TYPE 5
74#define NOUVEAU_GETPARAM_FB_SIZE 8
75#define NOUVEAU_GETPARAM_AGP_SIZE 9
76#define NOUVEAU_GETPARAM_CHIPSET_ID 11
77#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
78#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
79#define NOUVEAU_GETPARAM_PTIMER_TIME 14
80#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
81#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
82struct drm_nouveau_getparam {
83 uint64_t param;
84 uint64_t value;
85};
86
87struct drm_nouveau_setparam {
88 uint64_t param;
89 uint64_t value;
90};
91
92#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 28#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
93#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 29#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
94#define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 30#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
@@ -180,35 +116,19 @@ struct drm_nouveau_gem_cpu_fini {
180 uint32_t handle; 116 uint32_t handle;
181}; 117};
182 118
183enum nouveau_bus_type { 119#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
184 NV_AGP = 0, 120#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
185 NV_PCI = 1, 121#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
186 NV_PCIE = 2, 122#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
187}; 123#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
188 124#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
189struct drm_nouveau_sarea { 125#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
190};
191
192#define DRM_NOUVEAU_GETPARAM 0x00
193#define DRM_NOUVEAU_SETPARAM 0x01
194#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
195#define DRM_NOUVEAU_CHANNEL_FREE 0x03
196#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
197#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
198#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
199#define DRM_NOUVEAU_GEM_NEW 0x40 126#define DRM_NOUVEAU_GEM_NEW 0x40
200#define DRM_NOUVEAU_GEM_PUSHBUF 0x41 127#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
201#define DRM_NOUVEAU_GEM_CPU_PREP 0x42 128#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
202#define DRM_NOUVEAU_GEM_CPU_FINI 0x43 129#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
203#define DRM_NOUVEAU_GEM_INFO 0x44 130#define DRM_NOUVEAU_GEM_INFO 0x44
204 131
205#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
206#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
207#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
208#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
209#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
210#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
211#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
212#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) 132#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
213#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) 133#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
214#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) 134#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)