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authorDave Airlie <airlied@redhat.com>2008-05-28 20:09:59 -0400
committerDave Airlie <airlied@redhat.com>2008-07-13 20:45:01 -0400
commitc0e09200dc0813972442e550a5905a132768e56c (patch)
treed38e635a30ff8b0a2b98b9d7f97cab1501f8209e /include/drm/radeon_drm.h
parentbce7f793daec3e65ec5c5705d2457b81fe7b5725 (diff)
drm: reorganise drm tree to be more future proof.
With the coming of kernel based modesetting and the memory manager stuff, the everything in one directory approach was getting very ugly and starting to be unmanageable. This restructures the drm along the lines of other kernel components. It creates a drivers/gpu/drm directory and moves the hw drivers into subdirectores. It moves the includes into an include/drm, and sets up the unifdef for the userspace headers we should be exporting. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'include/drm/radeon_drm.h')
-rw-r--r--include/drm/radeon_drm.h749
1 files changed, 749 insertions, 0 deletions
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
new file mode 100644
index 000000000000..73ff51f12311
--- /dev/null
+++ b/include/drm/radeon_drm.h
@@ -0,0 +1,749 @@
1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 */
32
33#ifndef __RADEON_DRM_H__
34#define __RADEON_DRM_H__
35
36/* WARNING: If you change any of these defines, make sure to change the
37 * defines in the X server file (radeon_sarea.h)
38 */
39#ifndef __RADEON_SAREA_DEFINES__
40#define __RADEON_SAREA_DEFINES__
41
42/* Old style state flags, required for sarea interface (1.1 and 1.2
43 * clears) and 1.2 drm_vertex2 ioctl.
44 */
45#define RADEON_UPLOAD_CONTEXT 0x00000001
46#define RADEON_UPLOAD_VERTFMT 0x00000002
47#define RADEON_UPLOAD_LINE 0x00000004
48#define RADEON_UPLOAD_BUMPMAP 0x00000008
49#define RADEON_UPLOAD_MASKS 0x00000010
50#define RADEON_UPLOAD_VIEWPORT 0x00000020
51#define RADEON_UPLOAD_SETUP 0x00000040
52#define RADEON_UPLOAD_TCL 0x00000080
53#define RADEON_UPLOAD_MISC 0x00000100
54#define RADEON_UPLOAD_TEX0 0x00000200
55#define RADEON_UPLOAD_TEX1 0x00000400
56#define RADEON_UPLOAD_TEX2 0x00000800
57#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
58#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
59#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
60#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
61#define RADEON_REQUIRE_QUIESCENCE 0x00010000
62#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
63#define RADEON_UPLOAD_ALL 0x003effff
64#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
65
66/* New style per-packet identifiers for use in cmd_buffer ioctl with
67 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
68 * state bits and the packet size:
69 */
70#define RADEON_EMIT_PP_MISC 0 /* context/7 */
71#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
72#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
73#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
74#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
75#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
76#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
77#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
78#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
79#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
80#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
81#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
82#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
83#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
84#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
85#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
86#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
87#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
88#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
89#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
90#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
91#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
92#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
93#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
94#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
95#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
96#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
97#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
98#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
99#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
100#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
101#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
102#define R200_EMIT_VAP_CTL 32 /* vap/1 */
103#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
104#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
105#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
106#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
107#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
108#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
109#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
110#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
111#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
112#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
113#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
114#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
115#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
116#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
117#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
118#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
119#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
120#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
121#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
122#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
123#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
124#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
125#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
126#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
127#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
128#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
129#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
130#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
131#define R200_EMIT_PP_CUBIC_FACES_0 61
132#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
133#define R200_EMIT_PP_CUBIC_FACES_1 63
134#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
135#define R200_EMIT_PP_CUBIC_FACES_2 65
136#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
137#define R200_EMIT_PP_CUBIC_FACES_3 67
138#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
139#define R200_EMIT_PP_CUBIC_FACES_4 69
140#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
141#define R200_EMIT_PP_CUBIC_FACES_5 71
142#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
143#define RADEON_EMIT_PP_TEX_SIZE_0 73
144#define RADEON_EMIT_PP_TEX_SIZE_1 74
145#define RADEON_EMIT_PP_TEX_SIZE_2 75
146#define R200_EMIT_RB3D_BLENDCOLOR 76
147#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
148#define RADEON_EMIT_PP_CUBIC_FACES_0 78
149#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
150#define RADEON_EMIT_PP_CUBIC_FACES_1 80
151#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
152#define RADEON_EMIT_PP_CUBIC_FACES_2 82
153#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
154#define R200_EMIT_PP_TRI_PERF_CNTL 84
155#define R200_EMIT_PP_AFS_0 85
156#define R200_EMIT_PP_AFS_1 86
157#define R200_EMIT_ATF_TFACTOR 87
158#define R200_EMIT_PP_TXCTLALL_0 88
159#define R200_EMIT_PP_TXCTLALL_1 89
160#define R200_EMIT_PP_TXCTLALL_2 90
161#define R200_EMIT_PP_TXCTLALL_3 91
162#define R200_EMIT_PP_TXCTLALL_4 92
163#define R200_EMIT_PP_TXCTLALL_5 93
164#define R200_EMIT_VAP_PVS_CNTL 94
165#define RADEON_MAX_STATE_PACKETS 95
166
167/* Commands understood by cmd_buffer ioctl. More can be added but
168 * obviously these can't be removed or changed:
169 */
170#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
171#define RADEON_CMD_SCALARS 2 /* emit scalar data */
172#define RADEON_CMD_VECTORS 3 /* emit vector data */
173#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
174#define RADEON_CMD_PACKET3 5 /* emit hw packet */
175#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
176#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
177#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
178 * doesn't make the cpu wait, just
179 * the graphics hardware */
180#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
181
182typedef union {
183 int i;
184 struct {
185 unsigned char cmd_type, pad0, pad1, pad2;
186 } header;
187 struct {
188 unsigned char cmd_type, packet_id, pad0, pad1;
189 } packet;
190 struct {
191 unsigned char cmd_type, offset, stride, count;
192 } scalars;
193 struct {
194 unsigned char cmd_type, offset, stride, count;
195 } vectors;
196 struct {
197 unsigned char cmd_type, addr_lo, addr_hi, count;
198 } veclinear;
199 struct {
200 unsigned char cmd_type, buf_idx, pad0, pad1;
201 } dma;
202 struct {
203 unsigned char cmd_type, flags, pad0, pad1;
204 } wait;
205} drm_radeon_cmd_header_t;
206
207#define RADEON_WAIT_2D 0x1
208#define RADEON_WAIT_3D 0x2
209
210/* Allowed parameters for R300_CMD_PACKET3
211 */
212#define R300_CMD_PACKET3_CLEAR 0
213#define R300_CMD_PACKET3_RAW 1
214
215/* Commands understood by cmd_buffer ioctl for R300.
216 * The interface has not been stabilized, so some of these may be removed
217 * and eventually reordered before stabilization.
218 */
219#define R300_CMD_PACKET0 1
220#define R300_CMD_VPU 2 /* emit vertex program upload */
221#define R300_CMD_PACKET3 3 /* emit a packet3 */
222#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
223#define R300_CMD_CP_DELAY 5
224#define R300_CMD_DMA_DISCARD 6
225#define R300_CMD_WAIT 7
226# define R300_WAIT_2D 0x1
227# define R300_WAIT_3D 0x2
228/* these two defines are DOING IT WRONG - however
229 * we have userspace which relies on using these.
230 * The wait interface is backwards compat new
231 * code should use the NEW_WAIT defines below
232 * THESE ARE NOT BIT FIELDS
233 */
234# define R300_WAIT_2D_CLEAN 0x3
235# define R300_WAIT_3D_CLEAN 0x4
236
237# define R300_NEW_WAIT_2D_3D 0x3
238# define R300_NEW_WAIT_2D_2D_CLEAN 0x4
239# define R300_NEW_WAIT_3D_3D_CLEAN 0x6
240# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
241
242#define R300_CMD_SCRATCH 8
243#define R300_CMD_R500FP 9
244
245typedef union {
246 unsigned int u;
247 struct {
248 unsigned char cmd_type, pad0, pad1, pad2;
249 } header;
250 struct {
251 unsigned char cmd_type, count, reglo, reghi;
252 } packet0;
253 struct {
254 unsigned char cmd_type, count, adrlo, adrhi;
255 } vpu;
256 struct {
257 unsigned char cmd_type, packet, pad0, pad1;
258 } packet3;
259 struct {
260 unsigned char cmd_type, packet;
261 unsigned short count; /* amount of packet2 to emit */
262 } delay;
263 struct {
264 unsigned char cmd_type, buf_idx, pad0, pad1;
265 } dma;
266 struct {
267 unsigned char cmd_type, flags, pad0, pad1;
268 } wait;
269 struct {
270 unsigned char cmd_type, reg, n_bufs, flags;
271 } scratch;
272 struct {
273 unsigned char cmd_type, count, adrlo, adrhi_flags;
274 } r500fp;
275} drm_r300_cmd_header_t;
276
277#define RADEON_FRONT 0x1
278#define RADEON_BACK 0x2
279#define RADEON_DEPTH 0x4
280#define RADEON_STENCIL 0x8
281#define RADEON_CLEAR_FASTZ 0x80000000
282#define RADEON_USE_HIERZ 0x40000000
283#define RADEON_USE_COMP_ZBUF 0x20000000
284
285#define R500FP_CONSTANT_TYPE (1 << 1)
286#define R500FP_CONSTANT_CLAMP (1 << 2)
287
288/* Primitive types
289 */
290#define RADEON_POINTS 0x1
291#define RADEON_LINES 0x2
292#define RADEON_LINE_STRIP 0x3
293#define RADEON_TRIANGLES 0x4
294#define RADEON_TRIANGLE_FAN 0x5
295#define RADEON_TRIANGLE_STRIP 0x6
296
297/* Vertex/indirect buffer size
298 */
299#define RADEON_BUFFER_SIZE 65536
300
301/* Byte offsets for indirect buffer data
302 */
303#define RADEON_INDEX_PRIM_OFFSET 20
304
305#define RADEON_SCRATCH_REG_OFFSET 32
306
307#define RADEON_NR_SAREA_CLIPRECTS 12
308
309/* There are 2 heaps (local/GART). Each region within a heap is a
310 * minimum of 64k, and there are at most 64 of them per heap.
311 */
312#define RADEON_LOCAL_TEX_HEAP 0
313#define RADEON_GART_TEX_HEAP 1
314#define RADEON_NR_TEX_HEAPS 2
315#define RADEON_NR_TEX_REGIONS 64
316#define RADEON_LOG_TEX_GRANULARITY 16
317
318#define RADEON_MAX_TEXTURE_LEVELS 12
319#define RADEON_MAX_TEXTURE_UNITS 3
320
321#define RADEON_MAX_SURFACES 8
322
323/* Blits have strict offset rules. All blit offset must be aligned on
324 * a 1K-byte boundary.
325 */
326#define RADEON_OFFSET_SHIFT 10
327#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
328#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
329
330#endif /* __RADEON_SAREA_DEFINES__ */
331
332typedef struct {
333 unsigned int red;
334 unsigned int green;
335 unsigned int blue;
336 unsigned int alpha;
337} radeon_color_regs_t;
338
339typedef struct {
340 /* Context state */
341 unsigned int pp_misc; /* 0x1c14 */
342 unsigned int pp_fog_color;
343 unsigned int re_solid_color;
344 unsigned int rb3d_blendcntl;
345 unsigned int rb3d_depthoffset;
346 unsigned int rb3d_depthpitch;
347 unsigned int rb3d_zstencilcntl;
348
349 unsigned int pp_cntl; /* 0x1c38 */
350 unsigned int rb3d_cntl;
351 unsigned int rb3d_coloroffset;
352 unsigned int re_width_height;
353 unsigned int rb3d_colorpitch;
354 unsigned int se_cntl;
355
356 /* Vertex format state */
357 unsigned int se_coord_fmt; /* 0x1c50 */
358
359 /* Line state */
360 unsigned int re_line_pattern; /* 0x1cd0 */
361 unsigned int re_line_state;
362
363 unsigned int se_line_width; /* 0x1db8 */
364
365 /* Bumpmap state */
366 unsigned int pp_lum_matrix; /* 0x1d00 */
367
368 unsigned int pp_rot_matrix_0; /* 0x1d58 */
369 unsigned int pp_rot_matrix_1;
370
371 /* Mask state */
372 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
373 unsigned int rb3d_ropcntl;
374 unsigned int rb3d_planemask;
375
376 /* Viewport state */
377 unsigned int se_vport_xscale; /* 0x1d98 */
378 unsigned int se_vport_xoffset;
379 unsigned int se_vport_yscale;
380 unsigned int se_vport_yoffset;
381 unsigned int se_vport_zscale;
382 unsigned int se_vport_zoffset;
383
384 /* Setup state */
385 unsigned int se_cntl_status; /* 0x2140 */
386
387 /* Misc state */
388 unsigned int re_top_left; /* 0x26c0 */
389 unsigned int re_misc;
390} drm_radeon_context_regs_t;
391
392typedef struct {
393 /* Zbias state */
394 unsigned int se_zbias_factor; /* 0x1dac */
395 unsigned int se_zbias_constant;
396} drm_radeon_context2_regs_t;
397
398/* Setup registers for each texture unit
399 */
400typedef struct {
401 unsigned int pp_txfilter;
402 unsigned int pp_txformat;
403 unsigned int pp_txoffset;
404 unsigned int pp_txcblend;
405 unsigned int pp_txablend;
406 unsigned int pp_tfactor;
407 unsigned int pp_border_color;
408} drm_radeon_texture_regs_t;
409
410typedef struct {
411 unsigned int start;
412 unsigned int finish;
413 unsigned int prim:8;
414 unsigned int stateidx:8;
415 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
416 unsigned int vc_format; /* vertex format */
417} drm_radeon_prim_t;
418
419typedef struct {
420 drm_radeon_context_regs_t context;
421 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
422 drm_radeon_context2_regs_t context2;
423 unsigned int dirty;
424} drm_radeon_state_t;
425
426typedef struct {
427 /* The channel for communication of state information to the
428 * kernel on firing a vertex buffer with either of the
429 * obsoleted vertex/index ioctls.
430 */
431 drm_radeon_context_regs_t context_state;
432 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
433 unsigned int dirty;
434 unsigned int vertsize;
435 unsigned int vc_format;
436
437 /* The current cliprects, or a subset thereof.
438 */
439 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
440 unsigned int nbox;
441
442 /* Counters for client-side throttling of rendering clients.
443 */
444 unsigned int last_frame;
445 unsigned int last_dispatch;
446 unsigned int last_clear;
447
448 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
449 1];
450 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
451 int ctx_owner;
452 int pfState; /* number of 3d windows (0,1,2ormore) */
453 int pfCurrentPage; /* which buffer is being displayed? */
454 int crtc2_base; /* CRTC2 frame offset */
455 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
456} drm_radeon_sarea_t;
457
458/* WARNING: If you change any of these defines, make sure to change the
459 * defines in the Xserver file (xf86drmRadeon.h)
460 *
461 * KW: actually it's illegal to change any of this (backwards compatibility).
462 */
463
464/* Radeon specific ioctls
465 * The device specific ioctl range is 0x40 to 0x79.
466 */
467#define DRM_RADEON_CP_INIT 0x00
468#define DRM_RADEON_CP_START 0x01
469#define DRM_RADEON_CP_STOP 0x02
470#define DRM_RADEON_CP_RESET 0x03
471#define DRM_RADEON_CP_IDLE 0x04
472#define DRM_RADEON_RESET 0x05
473#define DRM_RADEON_FULLSCREEN 0x06
474#define DRM_RADEON_SWAP 0x07
475#define DRM_RADEON_CLEAR 0x08
476#define DRM_RADEON_VERTEX 0x09
477#define DRM_RADEON_INDICES 0x0A
478#define DRM_RADEON_NOT_USED
479#define DRM_RADEON_STIPPLE 0x0C
480#define DRM_RADEON_INDIRECT 0x0D
481#define DRM_RADEON_TEXTURE 0x0E
482#define DRM_RADEON_VERTEX2 0x0F
483#define DRM_RADEON_CMDBUF 0x10
484#define DRM_RADEON_GETPARAM 0x11
485#define DRM_RADEON_FLIP 0x12
486#define DRM_RADEON_ALLOC 0x13
487#define DRM_RADEON_FREE 0x14
488#define DRM_RADEON_INIT_HEAP 0x15
489#define DRM_RADEON_IRQ_EMIT 0x16
490#define DRM_RADEON_IRQ_WAIT 0x17
491#define DRM_RADEON_CP_RESUME 0x18
492#define DRM_RADEON_SETPARAM 0x19
493#define DRM_RADEON_SURF_ALLOC 0x1a
494#define DRM_RADEON_SURF_FREE 0x1b
495
496#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
497#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
498#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
499#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
500#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
501#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
502#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
503#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
504#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
505#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
506#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
507#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
508#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
509#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
510#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
511#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
512#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
513#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
514#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
515#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
516#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
517#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
518#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
519#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
520#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
521#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
522#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
523
524typedef struct drm_radeon_init {
525 enum {
526 RADEON_INIT_CP = 0x01,
527 RADEON_CLEANUP_CP = 0x02,
528 RADEON_INIT_R200_CP = 0x03,
529 RADEON_INIT_R300_CP = 0x04
530 } func;
531 unsigned long sarea_priv_offset;
532 int is_pci;
533 int cp_mode;
534 int gart_size;
535 int ring_size;
536 int usec_timeout;
537
538 unsigned int fb_bpp;
539 unsigned int front_offset, front_pitch;
540 unsigned int back_offset, back_pitch;
541 unsigned int depth_bpp;
542 unsigned int depth_offset, depth_pitch;
543
544 unsigned long fb_offset;
545 unsigned long mmio_offset;
546 unsigned long ring_offset;
547 unsigned long ring_rptr_offset;
548 unsigned long buffers_offset;
549 unsigned long gart_textures_offset;
550} drm_radeon_init_t;
551
552typedef struct drm_radeon_cp_stop {
553 int flush;
554 int idle;
555} drm_radeon_cp_stop_t;
556
557typedef struct drm_radeon_fullscreen {
558 enum {
559 RADEON_INIT_FULLSCREEN = 0x01,
560 RADEON_CLEANUP_FULLSCREEN = 0x02
561 } func;
562} drm_radeon_fullscreen_t;
563
564#define CLEAR_X1 0
565#define CLEAR_Y1 1
566#define CLEAR_X2 2
567#define CLEAR_Y2 3
568#define CLEAR_DEPTH 4
569
570typedef union drm_radeon_clear_rect {
571 float f[5];
572 unsigned int ui[5];
573} drm_radeon_clear_rect_t;
574
575typedef struct drm_radeon_clear {
576 unsigned int flags;
577 unsigned int clear_color;
578 unsigned int clear_depth;
579 unsigned int color_mask;
580 unsigned int depth_mask; /* misnamed field: should be stencil */
581 drm_radeon_clear_rect_t __user *depth_boxes;
582} drm_radeon_clear_t;
583
584typedef struct drm_radeon_vertex {
585 int prim;
586 int idx; /* Index of vertex buffer */
587 int count; /* Number of vertices in buffer */
588 int discard; /* Client finished with buffer? */
589} drm_radeon_vertex_t;
590
591typedef struct drm_radeon_indices {
592 int prim;
593 int idx;
594 int start;
595 int end;
596 int discard; /* Client finished with buffer? */
597} drm_radeon_indices_t;
598
599/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
600 * - allows multiple primitives and state changes in a single ioctl
601 * - supports driver change to emit native primitives
602 */
603typedef struct drm_radeon_vertex2 {
604 int idx; /* Index of vertex buffer */
605 int discard; /* Client finished with buffer? */
606 int nr_states;
607 drm_radeon_state_t __user *state;
608 int nr_prims;
609 drm_radeon_prim_t __user *prim;
610} drm_radeon_vertex2_t;
611
612/* v1.3 - obsoletes drm_radeon_vertex2
613 * - allows arbitarily large cliprect list
614 * - allows updating of tcl packet, vector and scalar state
615 * - allows memory-efficient description of state updates
616 * - allows state to be emitted without a primitive
617 * (for clears, ctx switches)
618 * - allows more than one dma buffer to be referenced per ioctl
619 * - supports tcl driver
620 * - may be extended in future versions with new cmd types, packets
621 */
622typedef struct drm_radeon_cmd_buffer {
623 int bufsz;
624 char __user *buf;
625 int nbox;
626 struct drm_clip_rect __user *boxes;
627} drm_radeon_cmd_buffer_t;
628
629typedef struct drm_radeon_tex_image {
630 unsigned int x, y; /* Blit coordinates */
631 unsigned int width, height;
632 const void __user *data;
633} drm_radeon_tex_image_t;
634
635typedef struct drm_radeon_texture {
636 unsigned int offset;
637 int pitch;
638 int format;
639 int width; /* Texture image coordinates */
640 int height;
641 drm_radeon_tex_image_t __user *image;
642} drm_radeon_texture_t;
643
644typedef struct drm_radeon_stipple {
645 unsigned int __user *mask;
646} drm_radeon_stipple_t;
647
648typedef struct drm_radeon_indirect {
649 int idx;
650 int start;
651 int end;
652 int discard;
653} drm_radeon_indirect_t;
654
655/* enum for card type parameters */
656#define RADEON_CARD_PCI 0
657#define RADEON_CARD_AGP 1
658#define RADEON_CARD_PCIE 2
659
660/* 1.3: An ioctl to get parameters that aren't available to the 3d
661 * client any other way.
662 */
663#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
664#define RADEON_PARAM_LAST_FRAME 2
665#define RADEON_PARAM_LAST_DISPATCH 3
666#define RADEON_PARAM_LAST_CLEAR 4
667/* Added with DRM version 1.6. */
668#define RADEON_PARAM_IRQ_NR 5
669#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
670/* Added with DRM version 1.8. */
671#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
672#define RADEON_PARAM_STATUS_HANDLE 8
673#define RADEON_PARAM_SAREA_HANDLE 9
674#define RADEON_PARAM_GART_TEX_HANDLE 10
675#define RADEON_PARAM_SCRATCH_OFFSET 11
676#define RADEON_PARAM_CARD_TYPE 12
677#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
678#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
679#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
680
681typedef struct drm_radeon_getparam {
682 int param;
683 void __user *value;
684} drm_radeon_getparam_t;
685
686/* 1.6: Set up a memory manager for regions of shared memory:
687 */
688#define RADEON_MEM_REGION_GART 1
689#define RADEON_MEM_REGION_FB 2
690
691typedef struct drm_radeon_mem_alloc {
692 int region;
693 int alignment;
694 int size;
695 int __user *region_offset; /* offset from start of fb or GART */
696} drm_radeon_mem_alloc_t;
697
698typedef struct drm_radeon_mem_free {
699 int region;
700 int region_offset;
701} drm_radeon_mem_free_t;
702
703typedef struct drm_radeon_mem_init_heap {
704 int region;
705 int size;
706 int start;
707} drm_radeon_mem_init_heap_t;
708
709/* 1.6: Userspace can request & wait on irq's:
710 */
711typedef struct drm_radeon_irq_emit {
712 int __user *irq_seq;
713} drm_radeon_irq_emit_t;
714
715typedef struct drm_radeon_irq_wait {
716 int irq_seq;
717} drm_radeon_irq_wait_t;
718
719/* 1.10: Clients tell the DRM where they think the framebuffer is located in
720 * the card's address space, via a new generic ioctl to set parameters
721 */
722
723typedef struct drm_radeon_setparam {
724 unsigned int param;
725 int64_t value;
726} drm_radeon_setparam_t;
727
728#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
729#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
730#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
731#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
732#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
733#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
734/* 1.14: Clients can allocate/free a surface
735 */
736typedef struct drm_radeon_surface_alloc {
737 unsigned int address;
738 unsigned int size;
739 unsigned int flags;
740} drm_radeon_surface_alloc_t;
741
742typedef struct drm_radeon_surface_free {
743 unsigned int address;
744} drm_radeon_surface_free_t;
745
746#define DRM_RADEON_VBLANK_CRTC1 1
747#define DRM_RADEON_VBLANK_CRTC2 2
748
749#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 09:57:56 -0500