drm/nouveau: Add DRM driver for NVIDIA GPUs

This adds a drm/kms staging non-API stable driver for GPUs from NVIDIA.

This driver is a KMS-based driver and requires a compatible nouveau
userspace libdrm and nouveau X.org driver.

This driver requires firmware files not available in this kernel tree,
interested parties can find them via the nouveau project git archive.

This driver is reverse engineered, and is in no way supported by nVidia.

Support for nearly the complete range of nvidia hw from nv04->g80 (nv50)
is available, and the kms driver should support driving nearly all
output types (displayport is under development still) along with supporting
suspend/resume.

This work is all from the upstream nouveau project found at
nouveau.freedesktop.org.

The original authors list from nouveau git tree is:
Anssi Hannula <anssi.hannula@iki.fi>
Ben Skeggs <bskeggs@redhat.com>
Francisco Jerez <currojerez@riseup.net>
Maarten Maathuis <madman2003@gmail.com>
Marcin Kościelnicki <koriakin@0x04.net>
Matthew Garrett <mjg@redhat.com>
Matt Parnell <mparnell@gmail.com>
Patrice Mandin <patmandin@gmail.com>
Pekka Paalanen <pq@iki.fi>
Xavier Chantry <shiningxc@gmail.com>
along with project founder Stephane Marchesin <marchesin@icps.u-strasbg.fr>

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 86 insertions, 0 deletions

diff --git a/include/drm/i2c/ch7006.h b/include/drm/i2c/ch7006.h
new file mode 100644
index 000000000000..8390b437a1f8
--- /dev/null
+++ b/include/drm/i2c/ch7006.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2009 Francisco Jerez.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __DRM_I2C_CH7006_H__
+#define __DRM_I2C_CH7006_H__
+
+/**
+ * struct ch7006_encoder_params
+ *
+ * Describes how the ch7006 is wired up with the GPU. It should be
+ * used as the @params parameter of its @set_config method.
+ *
+ * See "http://www.chrontel.com/pdf/7006.pdf" for their precise
+ * meaning.
+ */
+struct ch7006_encoder_params {
+        enum {
+                CH7006_FORMAT_RGB16 = 0,
+                CH7006_FORMAT_YCrCb24m16,
+                CH7006_FORMAT_RGB24m16,
+                CH7006_FORMAT_RGB15,
+                CH7006_FORMAT_RGB24m12C,
+                CH7006_FORMAT_RGB24m12I,
+                CH7006_FORMAT_RGB24m8,
+                CH7006_FORMAT_RGB16m8,
+                CH7006_FORMAT_RGB15m8,
+                CH7006_FORMAT_YCrCb24m8,
+        } input_format;
+
+        enum {
+                CH7006_CLOCK_SLAVE = 0,
+                CH7006_CLOCK_MASTER,
+        } clock_mode;
+
+        enum {
+                CH7006_CLOCK_EDGE_NEG = 0,
+                CH7006_CLOCK_EDGE_POS,
+        } clock_edge;
+
+        int xcm, pcm;
+
+        enum {
+                CH7006_SYNC_SLAVE = 0,
+                CH7006_SYNC_MASTER,
+        } sync_direction;
+
+        enum {
+                CH7006_SYNC_SEPARATED = 0,
+                CH7006_SYNC_EMBEDDED,
+        } sync_encoding;
+
+        enum {
+                CH7006_POUT_1_8V = 0,
+                CH7006_POUT_3_3V,
+        } pout_level;
+
+        enum {
+                CH7006_ACTIVE_HSYNC = 0,
+                CH7006_ACTIVE_DSTART,
+        } active_detect;
+};
+
+#endif