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authorJesse Barnes <jbarnes@virtuousgeek.org>2009-02-23 18:36:41 -0500
committerDave Airlie <airlied@linux.ie>2009-02-24 23:11:00 -0500
commitfe56cf45f951b3810313584605c1d8a4f20b33a4 (patch)
tree84b6c8bb6178e7ccd4a5fe890d0945b58ddff4f1 /include/drm/drm_edid.h
parentc8766ac5933d6ee75e7ce379a1eb5ceb451fcb83 (diff)
drm: Fix ordering of bit fields in EDID structure leading huge vsync values.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'include/drm/drm_edid.h')
-rw-r--r--include/drm/drm_edid.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index c707c15f5164..ff8d27af4786 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -58,10 +58,10 @@ struct detailed_pixel_timing {
58 u8 hsync_pulse_width_lo; 58 u8 hsync_pulse_width_lo;
59 u8 vsync_pulse_width_lo:4; 59 u8 vsync_pulse_width_lo:4;
60 u8 vsync_offset_lo:4; 60 u8 vsync_offset_lo:4;
61 u8 hsync_pulse_width_hi:2;
62 u8 hsync_offset_hi:2;
63 u8 vsync_pulse_width_hi:2; 61 u8 vsync_pulse_width_hi:2;
64 u8 vsync_offset_hi:2; 62 u8 vsync_offset_hi:2;
63 u8 hsync_pulse_width_hi:2;
64 u8 hsync_offset_hi:2;
65 u8 width_mm_lo; 65 u8 width_mm_lo;
66 u8 height_mm_lo; 66 u8 height_mm_lo;
67 u8 height_mm_hi:4; 67 u8 height_mm_hi:4;