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authorMichel Dänzer <daenzer@vmware.com>2009-06-15 10:56:07 -0400
committerDave Airlie <airlied@redhat.com>2009-06-18 19:11:13 -0400
commit0454beab0f6bc6d350860abd549b86959d2f6f40 (patch)
tree65b147779fe82a33339b0ec9978b051e0af6acff /include/drm/drm_edid.h
parent00fa28ae29f70c9f26023f9922c4d2e1ca1297e3 (diff)
drm: EDID endianness fixes.
Mostly replacing bitfields with explicit masks and shifts. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'include/drm/drm_edid.h')
-rw-r--r--include/drm/drm_edid.h92
1 files changed, 43 insertions, 49 deletions
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index a11cc9d32591..c263e4d71754 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -28,53 +28,49 @@
28#define EDID_LENGTH 128 28#define EDID_LENGTH 128
29#define DDC_ADDR 0x50 29#define DDC_ADDR 0x50
30 30
31#ifdef BIG_ENDIAN
32#error "EDID structure is little endian, need big endian versions"
33#else
34
35struct est_timings { 31struct est_timings {
36 u8 t1; 32 u8 t1;
37 u8 t2; 33 u8 t2;
38 u8 mfg_rsvd; 34 u8 mfg_rsvd;
39} __attribute__((packed)); 35} __attribute__((packed));
40 36
37/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
38#define EDID_TIMING_ASPECT_SHIFT 0
39#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
40
41/* need to add 60 */
42#define EDID_TIMING_VFREQ_SHIFT 2
43#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
44
41struct std_timing { 45struct std_timing {
42 u8 hsize; /* need to multiply by 8 then add 248 */ 46 u8 hsize; /* need to multiply by 8 then add 248 */
43 u8 vfreq:6; /* need to add 60 */ 47 u8 vfreq_aspect;
44 u8 aspect_ratio:2; /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
45} __attribute__((packed)); 48} __attribute__((packed));
46 49
50#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 6)
51#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 5)
52#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
53#define DRM_EDID_PT_STEREO (1 << 2)
54#define DRM_EDID_PT_INTERLACED (1 << 1)
55
47/* If detailed data is pixel timing */ 56/* If detailed data is pixel timing */
48struct detailed_pixel_timing { 57struct detailed_pixel_timing {
49 u8 hactive_lo; 58 u8 hactive_lo;
50 u8 hblank_lo; 59 u8 hblank_lo;
51 u8 hblank_hi:4; 60 u8 hactive_hblank_hi;
52 u8 hactive_hi:4;
53 u8 vactive_lo; 61 u8 vactive_lo;
54 u8 vblank_lo; 62 u8 vblank_lo;
55 u8 vblank_hi:4; 63 u8 vactive_vblank_hi;
56 u8 vactive_hi:4;
57 u8 hsync_offset_lo; 64 u8 hsync_offset_lo;
58 u8 hsync_pulse_width_lo; 65 u8 hsync_pulse_width_lo;
59 u8 vsync_pulse_width_lo:4; 66 u8 vsync_offset_pulse_width_lo;
60 u8 vsync_offset_lo:4; 67 u8 hsync_vsync_offset_pulse_width_hi;
61 u8 vsync_pulse_width_hi:2;
62 u8 vsync_offset_hi:2;
63 u8 hsync_pulse_width_hi:2;
64 u8 hsync_offset_hi:2;
65 u8 width_mm_lo; 68 u8 width_mm_lo;
66 u8 height_mm_lo; 69 u8 height_mm_lo;
67 u8 height_mm_hi:4; 70 u8 width_height_mm_hi;
68 u8 width_mm_hi:4;
69 u8 hborder; 71 u8 hborder;
70 u8 vborder; 72 u8 vborder;
71 u8 unknown0:1; 73 u8 misc;
72 u8 hsync_positive:1;
73 u8 vsync_positive:1;
74 u8 separate_sync:2;
75 u8 stereo:1;
76 u8 unknown6:1;
77 u8 interlaced:1;
78} __attribute__((packed)); 74} __attribute__((packed));
79 75
80/* If it's not pixel timing, it'll be one of the below */ 76/* If it's not pixel timing, it'll be one of the below */
@@ -88,18 +84,16 @@ struct detailed_data_monitor_range {
88 u8 min_hfreq_khz; 84 u8 min_hfreq_khz;
89 u8 max_hfreq_khz; 85 u8 max_hfreq_khz;
90 u8 pixel_clock_mhz; /* need to multiply by 10 */ 86 u8 pixel_clock_mhz; /* need to multiply by 10 */
91 u16 sec_gtf_toggle; /* A000=use above, 20=use below */ /* FIXME: byte order */ 87 __le16 sec_gtf_toggle; /* A000=use above, 20=use below */
92 u8 hfreq_start_khz; /* need to multiply by 2 */ 88 u8 hfreq_start_khz; /* need to multiply by 2 */
93 u8 c; /* need to divide by 2 */ 89 u8 c; /* need to divide by 2 */
94 u16 m; /* FIXME: byte order */ 90 __le16 m;
95 u8 k; 91 u8 k;
96 u8 j; /* need to divide by 2 */ 92 u8 j; /* need to divide by 2 */
97} __attribute__((packed)); 93} __attribute__((packed));
98 94
99struct detailed_data_wpindex { 95struct detailed_data_wpindex {
100 u8 white_y_lo:2; 96 u8 white_xy_lo; /* Upper 2 bits each */
101 u8 white_x_lo:2;
102 u8 pad:4;
103 u8 white_x_hi; 97 u8 white_x_hi;
104 u8 white_y_hi; 98 u8 white_y_hi;
105 u8 gamma; /* need to divide by 100 then add 1 */ 99 u8 gamma; /* need to divide by 100 then add 1 */
@@ -134,13 +128,29 @@ struct detailed_non_pixel {
134#define EDID_DETAIL_MONITOR_SERIAL 0xff 128#define EDID_DETAIL_MONITOR_SERIAL 0xff
135 129
136struct detailed_timing { 130struct detailed_timing {
137 u16 pixel_clock; /* need to multiply by 10 KHz */ /* FIXME: byte order */ 131 __le16 pixel_clock; /* need to multiply by 10 KHz */
138 union { 132 union {
139 struct detailed_pixel_timing pixel_data; 133 struct detailed_pixel_timing pixel_data;
140 struct detailed_non_pixel other_data; 134 struct detailed_non_pixel other_data;
141 } data; 135 } data;
142} __attribute__((packed)); 136} __attribute__((packed));
143 137
138#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 7)
139#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 5)
140#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 4)
141#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
142#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 2)
143#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 1)
144#define DRM_EDID_INPUT_DIGITAL (1 << 0) /* bits above must be zero if set */
145
146#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 7)
147#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 6)
148#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 5)
149#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
150#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 2)
151#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 1)
152#define DRM_EDID_FEATURE_PM_STANDBY (1 << 0)
153
144struct edid { 154struct edid {
145 u8 header[8]; 155 u8 header[8];
146 /* Vendor & product info */ 156 /* Vendor & product info */
@@ -153,25 +163,11 @@ struct edid {
153 u8 version; 163 u8 version;
154 u8 revision; 164 u8 revision;
155 /* Display info: */ 165 /* Display info: */
156 /* input definition */ 166 u8 input;
157 u8 serration_vsync:1;
158 u8 sync_on_green:1;
159 u8 composite_sync:1;
160 u8 separate_syncs:1;
161 u8 blank_to_black:1;
162 u8 video_level:2;
163 u8 digital:1; /* bits below must be zero if set */
164 u8 width_cm; 167 u8 width_cm;
165 u8 height_cm; 168 u8 height_cm;
166 u8 gamma; 169 u8 gamma;
167 /* feature support */ 170 u8 features;
168 u8 default_gtf:1;
169 u8 preferred_timing:1;
170 u8 standard_color:1;
171 u8 display_type:2; /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
172 u8 pm_active_off:1;
173 u8 pm_suspend:1;
174 u8 pm_standby:1;
175 /* Color characteristics */ 171 /* Color characteristics */
176 u8 red_green_lo; 172 u8 red_green_lo;
177 u8 black_white_lo; 173 u8 black_white_lo;
@@ -195,8 +191,6 @@ struct edid {
195 u8 checksum; 191 u8 checksum;
196} __attribute__((packed)); 192} __attribute__((packed));
197 193
198#endif /* little endian structs */
199
200#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 194#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
201 195
202#endif /* __DRM_EDID_H__ */ 196#endif /* __DRM_EDID_H__ */